LP8764-Q1: nRESETOUT GPIO10 value chagne via Register access

Hi Bala,

In principal yes, the idea has just been warm reset sequence would turn signal first low and then back to high after in the end of the sequence.

Br, Jari

Hello Jari

I have the following in my FSM. I do read that the WD_ERR_STATUS Register read 0xF2. But I do not see the nRSTOUT (GPIO10) asserted low.

I am asserting nRSTOUT But I am not seeing the RESET# ping go low. Why is that ?

Also, the Idea is to issue nRSTOUT while in WD_ERROR, without disturbing any of the power rails. While in that state, an external system manager CPU will intervene and either release the nRSTOUT (after capturing the I2C bus , do a write to MISC_REG and releasing it for the local CPU) or force it to STANDBY state by de asserting GPIO4 (This is an enable to the PMIC power sequencing) and then asserting GPIO to take the system back to ACTIVE state (No i2c access from the system manager cpu and the local Cpu has to read the interrupt register on boot and convey the system manager regariding a watchdog event. I hope this can be implemented. Please confirm. Thanks