UCC28700: Aux winding and Vcc question

Hi,

1 VDD  connect to VBLK through a resistor to provide initial startup current but after initial start power on, the current to VDD becomes much higher so to avoid high power losses the resistor value is high and not able to maintain VDD required bias current then this is resolved by the Vaud.

2 the diode is to rectifying the voltage from aux to dc which is required by VDD.

3 Discriminator is an analog circuit to help sensing and filtering the VS signal to determine Vout and several other monitored parameters. The datasheet page 13 has detailed sensing description.

Hi,

1. After power on if bias through a resistor to Vbulk the associated power losses are much higher than through the aux winding. So a design is made to bias from the aux and the resistor current small not sufficient to bias the ic.

2. when Vaux polarity as show by the dot is positive the diode will turn on to conduct, when that dot is negative then the diode off.

3. The description on page 13 and 14 is for the mechanism of how the discriminator to work. Please describe where you feel need to get additional explanation based on figure 13 to 15

Hi,

2. When the diode off, the CDD stored energy will bias the IC. CDD is charged up when the diode is on.

3. The best way to understand the discriminator is to understand Fig 13 to Fig 15 in the datasheet for you to use the IC. No matter what, you would have to first understand the three figures in order to know how the ic works.

The discriminator is based on analog although it is easier to describe it using some digital terminology.

4. The IC has both TINA and Spice so you can use either. Both software to run TINA or PSpice are free to use and free download from ti.com. 

Hi,

TLK is not calculated just set up a blanking time based on the typical application.

TSMPL is when VS p-p is within certain range 100mV then TSMPL timer starts, and roughly in about 200ns, if VS always within 100mV p-p, then at the end of 200ns, the IC sampler will sample that time instant VS value as the threshold then the discriminator just wait until VS sensed a roll-off compared to the sampled value about 0.5V to 0.75V, then that sampled value is treated as the secondary side output voltage, after compared this voltage to the VS voltage divider to determine next pulse termination threshold (peak current change or fsw change depending on where at the control law fig 15).

TDM is not calculated but = the above two addition while there is a max TDM about 0.425. If TDM reaches 0.425, then the discriminator will adjust duty cycle each cycle to keep TDM = 0.425 not increase anymore. So this IC can only operate in the DCM to the critical conduction mode (the last DCM before entering continuous conduction mode, CCM).

Hi,

The 100mV is peak to peak. The VS voltage from the divider is the setup for how much regulation achieve, the divider voltage is to compared to the internal reference voltage about 4V to decide if the secondary side output voltage is in regulation.

TDM max 0.425 is the reason the IC won't operate in CCM. 

Hi,

1. That is a process to determine the time that TDM ends together with the sampled value for discriminator to decide next cycle operation such as if TDM has reached 0.452, which portion law to use, etc.

2. Say, if the VS divider value is 3.8V, compared to the internal reference 4V, it means peak current needs to increase, or if peak current already at its max then fsw needs to increase. If VS divider value is 4.1V, then the fsw needs to reduce, or the peak current needs to reduce depending at which portion of the control law (fig 15)