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LP8764-Q1: Loading of NVM contents

Part Number: LP8764-Q1

I have two configurations

In both configurations, I enabling the watchdog in software (the MCU writes to address 0x12 register 0x09 from 0xBF to 0xFF)

On Watchdog Error, the MCU is provided with a RESET. But power is kept ON

GPIO4 is configured as Enable. 

To bring the MCU back, an external processor de asserts the GPIO4, and after a delay, asserts GPIO4. The MCU goes through a full power cycle.

On one system, the the PMIC register (dev add = 0x12, register address =09 comes up with  0xBF, while on another one, the value is 0xff after the GPIO4 de assert and assert sequence.)

I am asserting nRSTOUT and nRSTOUT_SOC during the Watchdog error as well as the power up sequence, at the end of which, both signals are de asserted.

What is the reason for this behavior ? Which setting should I be looking for ?

Thanks

Bala