TPS40305: BP to BOOT diode damage

Pete K 

Thank you very much for the question.

The most common cause of boot-diode failure we have seen with the TPS40305 has has actually been the selection of high-side MOSFETs with too much gate charge resulting in excessive diode current fusing the metal from BP to BOOT open, but that typically causes BOOT to be lower, not closer to BP.  A low reverse impedance from BOOT to BP would be an indication of a "failed short" damage to the BOOT diode.

When the BP to BOOT metallization fuses open:

BOOT may charge up very slowly, but HDRV will not rise with BOOT during the turn-on of the high-side FET.  HDRV will instead pull-up to BP.

This weak pull-up of HDRV will trigger high-side over-current, so the start up of the TPS40305 will contain several very narrow pulses on HDRV and possibly SW, as the high-side short circuit protection limits the on-time.

After a few pulses, the current limit will shut down switching and time-out for several soft-start periods before trying again.

If you see that start-up attempt, try added an external BP to BOOT diode.  If the circuit works normally with an external diode, the BP to BOOT metallization has been fused open.

A negative voltage on switch could cause a high BP to BOOT voltage and induce failure of the BOOT to SW diode.  The negative voltage on SW is induced by the parasitic inductances in the current path for the inductor current resonating with the parasitic capacitance of the switching node after the high-side FET turns off and the low-side FET turns on.  Since the turn-off of the high-side FET draws current out of the gate into HDRV, out SW and back to the source of the high-side MOSFET, the BOOT pin is not involved, so adding a boot resistor does not help.

The best way to reduce ringing is with a tight switching layout that minimizes the path of the dynamic currents that need to change paths between the high-side conduction period and the low-side conduction period so that there is as little energy for ringing as possible.  This involves maintaining a very tight loop between the input bypass capacitors, source of the synchronous rectifier (low-side FET) and the ground of the output capacitors.

Having small Drain of the Control FET (high-side FET) to Source of the Synchronous Rectifier (Low-side FET) bypass capacitance, with a self-resonance frequency matched to the ringing frequency and high enough ESR to be self-damping will typically mitigate switch node ringing.  typically an 0402 capacitor in 1nF - 10nF range is ideal with the higher the ringing frequency the smaller the ideal capacitance.

After layout improvements:

Adding a resistor in series with HDRV or SW however, will increase the turn-off time and thus reduce the negative ringing.

When adding a resistor to SW, it is best if the resistor is placed in series with the SW pin and the boot capacitor is connected to the switching node side such that the turn-on of the high-side FET does not include the SW capacitor, but includes the BOOT capacitor and HDRV resistor so that the turn-on and turn-off can be adjusted separately.

Alternatively, a properly sized and optimized snubber can absorb the switch node ringing energy and reduce the negative ringing.  I have attached a design spreadsheet to help optimize a snubber design.

1030.Snubber_Calculations.xlsx

It might also help if you are willing to share your schematic.