PTPS65931211RWERQ1 rev3 is in use, but not set up in the system
rev4 was ordered TI internal, but again rev3 was delivered. Meanwhile rev5 should be the newest.
We have received our first boards and work on the bring up. Review has been done prior to production by TI and necessary modifications has been considered. Compared to the EVM we use a different DDR4 and plan to use USB Boot. At the moment we face the following issues:
- JTAG - we do have basic connection to SOC, however, we cannot connect to any Core
- USB Boot - My PC recognizes the device and I can also start a transfer, but then there is an immediate reset. And it's not a HW reset (the line between PMCI and AM62A stays high). So apparently the boot ROM starts, but then the SoC is resetting.
So what kind of verification we can do? What are the minimum requirements to have USB boot working? (DDR init, Voltages, Sequence, clock, ...)
- We already have samples produced, so we would need to change to the new PMIC to be complaint to the specification, BUT would that solve our boot problem or do we have another issue?
Should USB Boot work with 0,75V or is this strictly not possible? - What is the difference between Rev.03 and Rev.04 and Rev.05 in terms of Voltage rail, Power Sequence and ROM Setting?
Is Rev5 the right revision to sample for AM62A24-1400 until TPS65224-Q1 is available in August?
Please align with processors colleagues (same thread title).
ciao
Hanno
