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LM51561H: 2 Enable thresholds at 0.5V and at 1.5V

Amir Cohen
Prodigy 20 points
Part Number: LM51561H

Hi,

As far as I understand the LM51561H has 2 enable levels at the UVLO/EN:

  • @0.5V Vcc is regulated to min(Vin,7V). The controller starts drawing current
  • @1.5V the controller starts pumping PWM and the converter starts working well. 

My issue is that I have a startup circuit that charges a cap on the BIAS pin. Once UVLO passes 0.5V and the controller starts drawing current the cap on the bias pin discharges and I never pass the 1.5V level UVLO and I never start pumping PWM. I'm stuck on the 0.5V level. Is there a way to disable the 0.5V enable level? to regulate Vcc and start pumping PWM at the same time once I pass 1.5V? 

Currently, I've solved the issue by using an external comparator connected to the UVLO such that when I exceed my desired voltage on the bias pin I set UVLO pin HIGH and immediately pass both UVLO thresholds and however this is not an ideal solution. 

Also, the DS doesn't state the current drawn by the controller when UVLO pin is between 0.5V and 1.5V.

  • 0
    TI__Guru 59755 points

    Hello Amir,

    Can you please share your circuit applied to BIAS and UVLO? How much current can be delivered by the circuit that charges BIAS?

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Prodigy 20 points

    Hi Brigitte,

    Thank you for your response. Unfortunately, I cannot share the circuit. I will try and explain as best as I can though: 

    I am using a voltage doubler and the output of the comparator I am using can supply ~1mA. I've also tested with a different comparator which can supply ~10mA. In both cases, the bias voltage still dropped once I passed the 0.5V enable threshold.

    I thought about using a driver to increase the current (CMOS fets at the output of voltage doubler comparator) but ultimately went with the solution of an additional comparator to sense bias externally and set UVLO above 1.5V immediately. Which works well. 

    If there is a clever way to disable the 0.5V  threshold (or have the controller draw less current) Or if there is to manufacture the component without the 0.5V threshold I could save on external comparator and peripherals.  

  • 0 in reply to Amir Cohen
    TI__Guru 59755 points

    Hello Amir,

    The device has a dual-level UVLO circuit. During power-on, if the BIAS pin voltage is greater than 2.7 V, and the UVLO pin voltage is in between the enable threshold (VEN) and the UVLO threshold (VUVLO) for more than 1.5 µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts.

    As soon as it starts, it will start to charge the capacitor on VCC through BIAS and I expect that this is the issue you are observing.

    I think your solution with pulling UVLO high faster is the best you could do or increase the current capability of the circuit on BIAS.

    BTW, just for curiosity, when the device is started, where does the supply for BIAS come from?

    In addition, even if it works with the 1mA comparator, I would recommend using the 10mA comparator instead for having some margin.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Prodigy 20 points

    Hi Brigitte,

    The bias comes from a standard startup circuit. Then the bias is supplied from a flyback winding. I'm definitely going for the 10mA comp. 

    Out of curiosity, typically controllers have 1 level of UVLO, in which everything is enabled simultaneously, internal LDOs and PWM output. I wonder why in this controller there are 2 levels? What are the advantages we get from it? 

    Best,

    Amir  

  • 0 in reply to Amir Cohen
    TI__Guru 59755 points

    Hello Amir,

    The advantage is that if you keep the device in between 0.5V and 1.5V on EN, the startup afterwards is shorter as the internal circuitry already started up. If this is an advantage for your system or not, depends on your requirements.

    Best regards,
    Brigitte