TPS51220: Vin voltage ripple

Far Hung 

I'm not sure what you mean by "define Vin voltage ripple" 

The input voltage ripple of a BUCK switching regulator will be determined by the charge demand of the switching - typicalled Iout x Vout./Vin x 1/Fsw  as the high-side FET conducts the full output current during the full high-side FET On-time, the input capacitance able to respond to the high-frequency pulse current (typically just the ceramic input capacitance) and the source impedance of the supply powering the input voltage (typically not fast enough to respond to the cycle by cycle pulsed input current)

When electrolytic input capacitors are used, the ceramic input capacitors need to be sized to limit the cycle by cycle input ripple voltage as to limit the RMS current flowing in the electrolytic capacitors' ESR in order to avoid overheating the electrolytic capacitors.  Vripple (pk-pk) = √3 x Irms(rated) x ESR  = 1.73 x Irms(rated) x ESR

For safety margin, most designers will limit Vripple(pk-pk) to Irms(rated) x ESR

When only Ceramic capacitors are used, it is generally good practice to limit the input ripple voltage to less than 250mV even if the capacitors and converter can tolerate it.

In addition to the Vin ripple voltage, it is a good idea to confirm that the input capacitors can tolerate the input RMS current.

For more details please see - https://www.ti.com/lit/an/slyt670/slyt670.pdf 

Far Hung 

I'm not sure what you mean by "define Vin voltage ripple" 

The input voltage ripple of a BUCK switching regulator will be determined by the charge demand of the switching - typicalled Iout x Vout./Vin x 1/Fsw  as the high-side FET conducts the full output current during the full high-side FET On-time, the input capacitance able to respond to the high-frequency pulse current (typically just the ceramic input capacitance) and the source impedance of the supply powering the input voltage (typically not fast enough to respond to the cycle by cycle pulsed input current)

When electrolytic input capacitors are used, the ceramic input capacitors need to be sized to limit the cycle by cycle input ripple voltage as to limit the RMS current flowing in the electrolytic capacitors' ESR in order to avoid overheating the electrolytic capacitors.  Vripple (pk-pk) = √3 x Irms(rated) x ESR  = 1.73 x Irms(rated) x ESR

For safety margin, most designers will limit Vripple(pk-pk) to Irms(rated) x ESR

When only Ceramic capacitors are used, it is generally good practice to limit the input ripple voltage to less than 250mV even if the capacitors and converter can tolerate it.

In addition to the Vin ripple voltage, it is a good idea to confirm that the input capacitors can tolerate the input RMS current.

For more details please see - https://www.ti.com/lit/an/slyt670/slyt670.pdf