Hi Jeff:
I have a questions to consult with you
Could you please help confirm what is the problem with my PCBLayout
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Jeff:
I have a questions to consult with you
Could you please help confirm what is the problem with my PCBLayout
Hi dxd,
Attached is my recommendation for layout with lowest EMI and best thermal. You may have to move a few component further out to meet design rules. It is also generally recommended to not power ground under an inductor as that creates a capacitor that spews EMI.
CPCB-1336 REV.G 20230712_jlf.PcbDoc
Regards,
Jeff
Hi Jeff
I'm glad to receive your suggestion. There are still some questions about PCBLayout that I would like to consult with you
Q1:Our PCB can only be single-sided mounted, so the modifications you made to me cannot be referenced. Could you please give me some more suggestions based on single-sided mounting?
Q2:I will delete the GND at the bottom of the inductor later. Are there any other areas of GND that need to be noted?
Hi dxd,
Regarding 1, you can use the same general placement, with the SW node via'ing down and back up. If you move the inductor further away, change some of the R's and C's to 402 footprint instead of 603, you can return the SW diode top. There are newer diodes in smaller packages with same current and voltage rating. The problem will be the BTST capacitor but with some shifting around of the components on the right side of the board, it is possible. The REGN to BTST is only need if you use 5V input.
Regarding 2, you want the input capacitors to have the shortest return path to IC GND as possible, without vias.
Regards,
Jeff