Other Parts Discussed in Thread: LM5069
Hi,
We are using LM5069-2 IC for hot swap application, below are the specs:
- Vin = 24V +/-10% tolerance
- Current Limit : 10A,
- Max load Capacitance : 2200uF
- Ta : 60C
- Power limit : 54W, Timer capacitor : 470nF
Q1: We are using LM5069_Design_Calculator_Rev C to perform the calculations, unfortunately not able to meet the SOA margin (A margin of >1.1 is required and a margin of >1.3 is recommended to account for the variation in the power limit and timer) considering ISC012N04LM6 MOSFET. Is this because of the power limit & timer capacitor selection? Attaching the file for reference. Since, we didn’t meet the derated SOA/Power limit TI recommends to use soft start control. Even then not able to meet the SOA margin!
Q2: Power limit dependency, we understand that IC determines the Pd by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to reduce the current in MOSFET. While the power limiting circuit is active, the fault timer is active. Right? Is the power limit dependent on the maximum power dissipation of the MOSFET? Meaning, should the power limit be less than max Pd of the MOSFET? What if it is limited close to max Pd of MOSFET
Q3: What is the maximum & minimum current limit that can be designed using LM5069-2 IC?
LM5069_Design_Calculator_Using ISC012N04LM6.xlsx