Can the GATE pin of LM5067 drive two MOSs, as there may be some differences between the two MOSs? Will driving both MOSs simultaneously result in one switch being faster and the other being slower?
If this chip can drive, how does the chip ensure equal driving current?
The setting of the currentlimit point ensures that the current of the MOS during the opening process does not exceed the currentlimit value we set. However, shouldn't Vds increase while the drain current is limited during the MOS opening process? According to Figure 9-5 (a), it decreases, how is this achieved?
