• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 4 answers
  • Subscribers 63 subscribers
  • Views 125 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LP5907-Q1: LP5907-Q1

Shreeharsha kandlaje
Prodigy 180 points
Part Number: LP5907-Q1
Other Parts Discussed in Thread: LP5907, TPS7A21-Q1,

LP5907 Q1 has max output cap limitation of 10uF.   is it allowed if i have high value of capacitor spread at longer distance from LDO output?

is there any guideliens regarding the 10uF value at what max distance i have to keep?

is it ok if i keep 10uF near LDO output and higher value at far distance?

  • 0
    TI__Expert 3810 points

    Hello Shreeharsha, 

    Unfortunately, we don't have any data with larger Cout than the one specified on the datasheet, therefore, cannot comment how the device might behave. For better performance it is recommended to place the input and output capacitors as close to the device as possible and on the same side of the PCB (more information on Section 10 Layout). 

    Shreeharsha kandlaje said:
    is it ok if i keep 10uF near LDO output and higher value at far distance?

    Even if 10uF are near the LDO output and the other capacitors are at a distance from the LDO it is still connected to the output of the LDO.

    Best,

    Eunize Tobias

  • 0 in reply to Eunize Tobias
    Prodigy 180 points

    hello Tobias,

    thank you for quick response.

    i read in some other question related to output capacitor that, LDO may go unstable if we put more than 10uF.  Also there is additional requirement of ESR at output of LDO. datasheet screenshot is shown below.

    Query:

    What is the frequency range for this ESR limit defined?

    background :

    LDO output is connected to processor power pins with multiple MLCC caps. Total value near 100uF. Also the dynamic impedance for those pins are higher value ( based on dynamic load current spec and allowed voltage range for the pin).

  • 0 in reply to Shreeharsha kandlaje
    TI__Expert 3810 points

    Hello Shreeharsha,

    Correct, LDO might not be stable, however we don't have any data to support this.

    The ESR frequency range is within the bandwidth of the LDO.

    Have you considered using a newer LDO with a higher Cout max? A good alternative would be TPS7A21-Q1. It is spec to be stable with Cout max 200uF.

    Best,

    Eunize Tobias

  • 0 in reply to Eunize Tobias
    Prodigy 180 points

    hello Tobias,

    could you please confirm the bandwidth of LP5907?

    i couldnt find it specifically mentioned in datasheet.

  • 0 in reply to Shreeharsha kandlaje
    TI__Expert 3810 points

    Hello Shreeharsha,

    The ESR is within the bandwidth of the LDO up to point on the capacitor's impedance curve where the capacitor's impedance becomes inductive (high frequencies). Capacitor manufacturers usually have online tools that calculate the impedance across frequency. Please review the capacitor impedance curve, identify the minimum impedance in that curve across frequency and evaluate if it is greater than the minimum ESR listed in LP5907-Q1 datasheet. Please let me know if this makes more sense.

    Best,

    Eunize Tobias

  • 0 in reply to Eunize Tobias
    Prodigy 180 points

    Hello Tobias,

    thank you for detailed reply.

    i am aware of the procedure to check this.

    however my question is slightly different- ie, Till what frequency( bandwidth of LDO) we need to verify this?

  • 0 in reply to Shreeharsha kandlaje
    TI__Expert 3810 points

    Hello Shreeharsha,

    The bandwidth of the LDO usually is between 100kHz-300kHZ. It is difficult to give an exact bandwidth especially for older devices.

    Best,

    Eunize Tobias