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TPS51206: Non DDR application, simple Vtt needed for SPI Flash termination

Mark Meyerhofer
Prodigy 40 points
Part Number: TPS51206

I'm looking to have an active termination on a QPI SPI Flash interface that is 4-bits wide with a clock line and a chip select line.  The TPS51206 looks line a cost effective solution for my intended use, even though it's not a DDR application.

I'm running at a lower frequency, 133MHz, than the DDR speeds that this part is designed for.  For purposes of this question, let's say that all six termination resistors are 49.9 ohms each and tied in common to the Vtt output.  Inputs VDD, VDDQSNS, VLDOIN are connected to 3.3V, with S3 and S5 pulled up to VDD (3.3V) using independent resistors.  The output driving the SPI flash is a 3.3V SPI Flash master controller that is part of the microprocessor.  Assuming all appropriate valued capacitors are connected as described in the specification:

1. Am I correct that my Vtt output voltage will be 1.65V, or 1/2 of 3.3V?

2. Am I allowed to tie the voltage regulator side of the termination resistors all together as a group?  Assume for this discussion that the termination resistors are 49.9 ohms.

3. After looking through 10 pages of Q&As, it looks like the above connections, for S3 and S5, will not be a problem with a common supply voltage of 3.3V that also feeds the power inputs and the VDDQSNS sense input.  Is my understanding correct?

3. So, given the small number of signal lines being terminated, the source or sink of the regulator will be less than 200mA in magnitude and seems within the specs of the part.  Is this correct?

4. Since there appears to be extra current capacity, could I also terminate an additional 6 other similar signal lines, from a second serial flash, using the the same regulator's Vtt?

Thank you for taking these questions.

  • 0
    TI__Genius 17355 points

    Hi Mark,

    1) Yes, the TPS52106 should output half of the VDDQSNS voltage which would be 3.3V/2 = 1.65V. This device utilizes active termination which results in tighter VTT output control and power dissipation. Specifically, Figures 9 through 12 in the datasheet give a good look at what to expect from the VTT regulation (cross reference with specs in Section 6.5).

    2) As long as the worse case current source / sink in this situation is within the +/- 2A specification for this part, I don't see an issue with the described configuration.

    3) Since S3 and S5 are control pins, you will want to make sure they receive a stable voltage that doesn't dip below the HIGH input logic level during expected operation. According to Figure 26 in the datasheet, transient response on VDDQ shouldn't impact S3 or S5 severely so I don't see an issue here.

    4) If 200mA is the expected worst case current from the termination resistors, this would still fall within the +/- 2A spec.

    5) As far as I know, you can tie more signal lines to the VTT output as long as the current capability of the termination regulator isn't exceeded.

    Regards,

    James