Dear Sir,
Could you please share test conditions as below for thermal information?
1. PCB layer
2. test pattern area
3. Oz for Cu
Best Regards,
Thomas
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Dear Sir,
Could you please share test conditions as below for thermal information?
1. PCB layer
2. test pattern area
3. Oz for Cu
Best Regards,
Thomas
Hi Thomas,
The thermal measurements for this part were likely taken on a 1s or 2s2p board in compliance with the EIA/JESD51-1, -2, -5, -6, -7, and -9 documents.
Looking at JESD51-9, I've provided the board sizes and oz below. If more detail is needed I suggest reading the Semiconductor and IC Package Thermal Metrics document linked in the datasheet for the testing methods.
Regards,
Henry
Hi Thomas,
What is the application? I believe the thermal values will change depending on your layout. I believe the best way to gauge thermal performance is to measure the thermals from the EVM with the device running to your design parameters.
Regards,
Henry
Hi Thomas,
I will contact the systems engineers for this device and see what they reply.
Thanks for your patience,
Henry
Hi Thomas,
Thank you for your patience, I've received info that it was tested on a High-K Jedec board which is a 4-layer, so it is probably the 2p2s board.
Regards,
Henry