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TPSM8D6C24: Design review

Part Number: TPSM8D6C24

Hi

 The design is DC/DC from input 5.5V and output 0.95V , Current 46A. A and B connected tougher 

I need help in Design review and need layout support

Please attach file my design and please review and comments

As I understand that AGND and PGND are connected inside the component so I don't need to connect them externally in one point 

from datasheet section 10.1 Layout Guidelines : "Those components can be terminated to AGND with a minimum return loop or bypassed to the copper area of a separate low-impedance analog ground (AGND) that is isolated from fast switching voltages and current paths and has single connection to PGND on the thermal pad through the AGND pin"

Because I using with the two parts of the DC/DC (to get 46A) I need to connect the AGND_A and AGND_B together, So what is the best way to short them to get minimum return loop and to be isolated from fast switching?.

  

Thanks

  • Itzik,

    I am assigning this to Nancy Zhang, the lead applications engineer for the TPSM8D6C24 for the full review.

    Because I using with the two parts of the DC/DC (to get 46A) I need to connect the AGND_A and AGND_B together, So what is the best way to short them to get minimum return loop and to be isolated from fast switching?.

    AGND_A and AGND_B do not need to be connected externally, they will be connected together through PGND.

    The resistor from MSEL2_B should go to AGND_B.

    The resistors from MSEL1_A, MSEL2_A, VSEL_A, and ADRSEL_A  should go to AGND_A.

    AGND_A and AGND_B should not be connected to the system ground.

  • Hi Itzik,

    As Peter said as above. AGND_A and AGND_B don't need to be connected externally.

    1. Separate pin 21 and Pin27 to be AGND_A and AGND_B

    2. Connect MSEL1_A, MSEL2_A, VSEL_A and ADESEL_A to AGND_A (R498/R499/R500)

    3. Connect MSEL2_B to AGND_B (R497).

    4. Remove D64 and just up pull up with R495

    5. R498 should be 26.1k for 0.95V output setting.

    6. C891 should be 100pF

    7. Output feedback should be as below by adding local sense and remote sense,

    8. The PCB Vin, PGND and VOUT copper should be as below.

    9. Please refer to TPSM8D6C24EVM-2PH EVM user's guide in the link as below. This is pretty similar to your design.

    https://www.ti.com/product/TPSM8D6C24?keyMatch=TPSM8D6C24&tisearch=search-everything&usecase=GPN-ALT

    Thanks,

    Nancy

  • Hi Itzik,

    VSEL_A top resistor R1306 should be open for 0.95V output setting. See below ad red highlighted from design tool.

    Thanks,

    Nancy

  • Thanks for your answer

    One issue about the Vsense.

    The Vosns_A and Gosns connected to my FPGA as a following:

    from to DC/DC via filter to 

    The filter that I did is still correct or i still need toimplement according to user guide?

    What is the meaning of local sense and remote sense do I need this?

    Where is the best placement of the filte close to the souce or destination?

     

    Thanks

  • Hi Itzik,

    Please see the connection we recommended for remote sense and local sense as below. 

    1. For remote sense, we recommend series with 2x10ohm resistors. These 2x10ohm resistors provide an impedance for C28 (between VOSNS and GOSNS) to react with to remove high-frequency noise from remote sense. They also provide node-breaking to control where sense points connected to the output and GND to provide a controlled regulation point. C28 must be placed near IC pins. Those 2x10ohm resistors can be placed near remote sense area of FPGA socket.

    2. For local sense, the main purpose is for safety of single fault. If the remote sense is open for some reasons, the device still can operate properly since local sense is connected. The local sense resistors can be placed near IC and output capacitor area. 

    Hope this helps,

    Thanks,

    Nancy