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UCC20225-Q1: dynamic dead time

Andrei Bucsa
Prodigy 10 points
Part Number: UCC20225-Q1
Other Parts Discussed in Thread: UCC20225

Dear Sir/ Madame,

I intend to use UCC20225 in some of our application, but I had a special requirement to control the dead time (DT) with a microcontroller.

The dead time is usually set with a variable resistors, but as I need a wide range of DT, a digital pot will not work for me and the control shall be voltage or current instead.

Now, the dead time circuitry is a black box in the data sheet.

My question is: can you please share the DT circuitry digram in order to make the adjustment with a circuitry that include an external DAC?

Looking forward to your feedback,

Thanks and Best Regards,

Andrei

  • 0
    TI__Genius 15756 points

    Hi Andrei,

    The real-time bandwidth of the DT pin is usually a problem due to noise, but I am glad that you find it to be a useful feature!

    The input is a current mirror. If it measures lower current, it registers a longer blanking time, which starts with the falling edge of the opposite input to configure deadtime. The input voltage is therefore ~0.7V.

    You might be able to control the DT input with an amplifier on the opposite side of the DT resistor. Raising that voltage would lower the current and probably increase the deadtime. You should still maximize the DT capacitance for filtering (100nF), since noise is a huge concern for this pin, especially for high deadtime settings.  

    The max deadtime I was able to achieve reliably was about 1.6us, which is hopefully a sufficient range for your application.

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Prodigy 10 points

    Sean, thank you for your reply. Most Appreciated!

    Can you please clarify how the current mirror is configured? Based on the fact that resistor is to the ground I assume the mirror sourcing current (outside through the resitor). Based on the fact that pin voltage to ground is about 0.7V I could assume the mirror bias (build with P MOSFETs or PNPs) is around 1.x volts. Can you please confirm?

    If this is the case, I can eventually use another mirror built with NPNs and a resistor to achieve a voltage controlled DT (so will be pure current sinking to ground from this pin).

    More questions arise in term of noise? How this reference current, set by an external resistor, is sampled? The DT is a result of current averaging through this pin?

    Can you please provide a block drawing of DT input? What is the current range and what is maximum theoretically achievable DT is the input had no noise?

    A sketch of input circuitry can be very helpful, so I can share then the propose implementation drawing...

    Most Appreciate your feedback,

    Best Regards,

    Andrei

  • 0 in reply to Andrei Bucsa
    TI__Genius 15756 points

    Hi Andrei,

    While I do not have the schematic to share, a pmos current mirror sounds about right. I think you can just treat it as a 0.7V source that measures output current.

    Max theoretical I think is 5us, but that's not what I measured.

    The current sampling is instantaneous, not an average, which leads to the noise sensitivity. However, it will lead to a good bandwidth for you application.

    Why are you trying to dynamically adjust deadtime?

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Prodigy 10 points

    The DT will range from 100ns to 3us.

    The proposed schematic is as below. Can you please provide the f(I) function?

    Thanks again,

    AndreiUCC20225.pdf

  • 0 in reply to Andrei Bucsa
    TI__Genius 15756 points

    Hi Andrei,

    I don't have access to simulation models with that level of detail. But I have heard of customers using current mirrors on this pin when automotive requirements forbid resistor sizes above 300k Ohms.

    3us might be an ambitious target for this device. I would suggest ordering a EVM and testing this theory before designing a PCB.

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    Prodigy 10 points

    Thanks Sean,

    As is not documented in the datasheet, can you please ask internally if there is an equation that determine DT as function of sourced current?

    As it is not safe to test-it and treated-it as a black box because there are chances to work for the test IC and for the rest do not work.

    Thanks again,

    Andrei

  • 0 in reply to Andrei Bucsa
    TI__Expert 3943 points

    Hi Andrei,

    Our expert Sean is currently Out of Office. We'll get back to you soon. Appreciate your patience and understanding.

    Best,

    Pratik

  • 0 in reply to Andrei Bucsa
    TI__Genius 13650 points

    Hi Andrei,

    The gate driver DT pin has a typical voltage of 0.8V. With this voltage and dead time equation in the datasheet we can come up with a dead time equation that can be used based on current:

    DT(ns) = 10 * RDT(kΩ)

    VDT(V) = 0.8V

    RDT(kΩ) = VDT(V) / IDT(mA) = 0.8V / IDT(mA)

    DT(ns) = 10 * 0.8V / IDT(mA) = 8 / IDT(mA)

    Final equation would be DT(ns) = 8 / IDT(mA) where DT would be in nanoseconds and IDT would be in mili-amps.

    As Sean mentioned I would suggest ordering an EVM and testing this before designing a PCB

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 10 points

    Hi Andy,

    Thank you for your answer. I did that calculation myself. All what I have now as feedback, confirms one datasheet paragraph and no more. Slight smile

    I want just to understand what the internal topology is. What I can assume is that DT is a function of current (a circuit that charge and discharge an internal capacitor, when an input transition happens to generate the linear delay and a comparator with a reference voltage). Now if a fraction of the same bias voltage is used as comparator voltage reference it might be ok if you set the current through an external resistor, because being a ratiometric setting so, probably doesn't matter to much.

    Now if it's a function of only current and an internal capacitance value (which I wish to be) this will be fine for me because if the external current is accurate (and circuitry work under 0.8V which can be a case for a current mirror) the DT will be also accurate and and consistent in time.

    So, can you confirm the DT depends only by sourced current through DT pin and not by this ~0.8V biasing voltage (or temperature, or other factors)? I don't care if needs to be trimmed, just to be consistent over the working temperature range.

    Looking forward to your feedback,

    Best Regards,

    Andrei

  • 0 in reply to Andrei Bucsa
    TI__Genius 13650 points

    Hi Andrei,

    The total DT would be affected by tolerance in the biasing voltage, temperature, and process variation of the gate driver. However, the biasing voltage tolerance and all other errors are included in the DT tolerance listed in the electrical characteristic table.

    With these additional resistor values and tolerances below you can assume the DT tolerance across current already accounting for temperature and process variation:

    • RDT = 10kOhms
      • Min = 80ns; Typ = 100ns; Max = 120ns
    • RDT = 20kOhms
      • Min = 160ns; Typ = 200ns; Max = 240ns
    • RDT = 50kOhms
      • Min = 400ns; Typ = 500ns; Max = 600ns

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 10 points

    Hi Andy,

    So, this means, the variation is linear and with resistor outside the tolerance is +-20%. My question still remain and is related to the internal topology (as the external control circuitry will be not the one recommended in the datasheet).

    To simplify, the external current control (instead of using a resistor which drawn a current from a bias supply) will worsen or will improve this tolerance?

    If is not too difficult, can we ask please the chip designer? Maybe this will help also others that want to use this feature to increase for example the switching efficiency.

    Thanks again and Most Appreciate your support,

    Best Regards,

    Andrei

  • 0 in reply to Andrei Bucsa
    TI__Genius 13650 points

    Hi Andrei,

    Yes, DT has a linear relationship with the resistance which would directly translate to having a linear relationship with current.

    We do not typically publicly share detailed internal circuitry of our gate drivers. Due to not characterizing the gate driver with the control circuitry you are trying to achieve we have to use the data we have available. Based on the information we have the tolerance with current control and resistor based would be same since they would only account for gate driver internal errors/tolerances/process-variations.

    Best regards,

    Andy Robles