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LMG3522R030: Thermal Model (PLECS)

Nicolas Schnyder
Prodigy 10 points
Part Number: LMG3522R030

Hi Everyone,

I have downloaded the PLECS simulation model of the LMG3522R030 device and thereby I obtained remarkably low temperature rise of the GaN FET.

For test purpose, I checked the behaviour with a simple Buck configuration (switching frequency 100 kHz), as it can be seen in the attached PLECS model. Thereby, switching 78 [A] at 400 [V] results in a junction temperature rise of only around 6 [°C] (for the high-side GaN FET). On the other hand, the calculation of conduction and switching losses seem to be coherent.

Hence, I checked the thermal description, whereas the following model parameters are present in the LMG352xR030_V1.xml file (attached as well):

FET:

sum(Ri_fet) = 0.056618 [K/W]

DIODE:

sum(Ri_diode) = 0.158798 [K/W]

One can see that the sum of the thermal resistors is not equal to the steady state thermal resistance of 0.28 [K/W] indicated in the datasheet.

Finally, my questions are:

  1. May there be a bug in the thermal description LMG352xR030_V1.xml?
  2. Additionally, I have seen that in the FET's Turn-Off Losses Look-Up Table, the turn-off energy Eoff = f(v,i,T) is only specified for fixed v = 400 [V] and T = -40 [°C]. Is it planned to provide more information in there?

Already thanks for the support and kind regards,

Nicolas

03b_DUT_LMG3522R030.zip

  • +1
    TI__Expert 5615 points

    Hi Nicolas,

    I see the thermal section in the xml file you are referring to. It looks like you are correct. The thermal resistance for this xml file adds up to ~0.05 C/W and it should be ~0.28C/W. This is an area I have marked down to correct in the next revision of the models. In the meantime, will reach out to our package team to get the correct foster model for this device and I will send you an email update once I hear back from them with the correct data. In addition to this the 0.28 C/W thermal resistance is for conduction, in order for this to be accurate in PLECs there must be a heat sink connected to the device with its own thermal resistance. These numbers will sum together (along with the thermal interface material thermal resistance) to be the systems thermal resistance.

    For the FET turn-off loss, our devices have extremely low turn-off as the eCoss will be included in the turn-on energy and with our integrated gate driver turn-off can occur as fast as possible to minimize overlap loss on turn-off. Due to this the turn-on losses will dominate the switching losses. I will look to add more temperature range in the next revision however, this number will not greatly change switching losses.

    Best,

    Kyle Wolf

  • 0 in reply to Kyle Wolf
    Prodigy 10 points

    Hi Kyle,

    Many thanks for your quick reply.

    Best regards,

    Nicolas