TPSM8D6C24: Inquiry regarding core power design that requires high power

JH Shin

JH Shin said:

1. What is the difference in efficiency between Case-A1 and Case-A2?

In general, Case A1 will have higher efficiency due to the lower currents flowing in each leg and the ability of each leg to have a higher percentage of inductor ripple due to additive ripple cancelation at the output resulting from the phase shift between the ripples.  It is also, in general, fair easier to find reasonably sized and high efficiency 20A inductors than 80A inductors with 1/4 the DCR

In fact, some of the lowest DCR inductors available on the market today are targeting the 20-30A / phase space, such as the SLC7530S series from Coilcraft with 0.129mΩ, lower than what is available in an 80-90A inductor.

JH Shin said:

    If the conditions are the same, which case has the advantage in terms of efficiency, and is there any data comparing it in approximate numbers?

The exact comparisons depend heavily on other constraints, like the aforementioned inductor restrictions and loading current requirements, but several percentage points are typical at 80A.

JH Shin said:

2. Is there a difference in reliability between Case-A1 and Case-A2?

In general, Case A2, with fewer overall components will have higher reliability unless Case A1 is designed with redundancy in mind, which most do not.  However, the lower peak currents and lower temperatures provided by practical designs in Case A1 tend to result in higher "real world" reliability despite the higher number of individual components and single point failure.

JH Shin said:

3. Between Case-A1 and Case-A2, which case is better in terms of heat generation? If you have any example materials, please share them.

Case A1 typically generates lower peak device temperatures by spreading heat generation over a wider area and by lower over all thermal power dissipation.  Case A2 has power loss concentrated in a single MOSFET bridge and single inductor, making heat spreading and thermal resistance generally higher.  Case A1 has the power loss spread out over a larger number of  components and wider area, allowing for lower overall heat generation and lower peak component temperatures.

JH Shin said:

4. In case of Case-A1, are there any specification limit issues in design, operation, and use when using the Adaptive / dynamic voltage scaling function?

Specification limit issues are generally part, not topology specific.  The primary challenge in the Case A1 design is current balancing.  This is typically accomplished by having one of the DC/DC converters operate the voltage control loop and having the other DC/DC converters track or follow it with some form of load sharing loop.

In the TPSM8D6C24, this is accomplished by Device 0 (Stack Controller) providing the voltage regulation loop and sharing the VSHARE voltage across the other devices and each DC/DC controller power stage using the VSHARE voltage as its target  SW output current.  This provides exceptional, high bandwidth current sharing among the phases with no issues with dynamic voltage regulation.

JH Shin said:

5. How will it work if one or more of the four parts in Case-A1 is defective?

Without specific high-reliability / redundancy designs, in most cases, Case A1 will stop generating an output if 1 or more devices are defective.  The TPSM8D6C24 is not designed with these specific high-reliability / redundancy features.

JH Shin said:

6. Are there many cases where Case-A1 has been used and proven in the field?

Yes.  Case A1 has been the most commonly uses CPU core power solution in the personal computing, notebook, enterprise and server computing markets for about 20 years.  As more and more processor loading currents exceed 30-40A levels, Case A1 is becoming more and more common.  Even in lower power Cellular smart phones, multi-phase power is becoming more and more common to allow smaller inductors and higher switching frequencies to reduce size and improve efficiency.

For more information on the benefits of multi-phase design: https://e2e.ti.com/blogs_/b/powerhouse/posts/powerlab-notes-when-to-choose-multiphase 

JH Shin 

The optimal  solution among these three cases is going to depend on a lot of factors, especially volume use of shared components with other solutions, as well as what you mean by the separate DC/DC controllers, specifically as that applies to the differences between Case A1 and B1.

Unless you are talking about differences in the number of independent voltage regulation loops, which is not highlighted in your graphics in any way, there is no difference between Case A1 and Case B1, so if you could let me know what your THINK the differences are, that might help me provide advice.

At 80A, the most optimal solution is likely a 3-phase solution rather than a 4-phase solution, unless the 20A power stages are heavily reused in other applications, leading to volume discounts on the 20A components.

40A power stage phases are on the upper end of price and efficiency optimization, with 25-30 being about the "sweet spot"   Case B2 will typically be slightly smaller and less expensive than A1 or B1, but less efficient.  A2 will be the smallest, but lowest efficiency.  Due to limited markets for 80A single phase power solutions, it will generally also be more expensive.

JH Shin 

If the SoC needs two independently controlled 40A supply voltages, Two 40A single phase power supplies will generally be lower cost and smaller than two independent 2-phase power supplies at 20A per phase, but the two, 2-phase power supplies will generally be more efficient with lower thermal stress on the components.

If the two SoC supplies can be supplied by a single source, rather than needing to be independent, a single 3-phase supply will likely be a better optimization.

JH Shin 

I2C is a basic, multi-controller / multi-target, two wire interface for chip to chip communication within a PCB board.  It can support speeds up to 1MHz using open drain drivers and pull-up termination.  It has the advantages of being a simple, broadly compatible two-wire, moderate power communications bus that is extremely flexible in that the meaning of any of the data bytes is not defined, and thus can be defined as best fits the target application of the DC/DC converter.

SMBus or System Management Bus was built on the foundations of I2C, but added more standardization and robustness with features like Packet Error Check (PEC) clock low time-out, and defined data and transaction types.  SMBus Also added an Out of Band ALERT feature, so a device could notify the system controller that it had information for it using a separate interrupt.  Alert Response Address, to allow the system to determine which device was asserting ALERT when many devices were asserting ALERT, ARP or address resolution protocol, which allows the systemt to dynamically assign addresses to devices on the bus.  SMBus was originally developed for the Smart Battery market, but continues to be a popular extention to I2C thanks to its improved reliability features.

PMBus or Power Management Bus is built on, and uses SMBus protocols, gaining all of it's advantages over I2C, but goes further to define what command address specific data is located at, and how that data is formatted with a specific mind for Power Management.  While this is more restrictive than I2C or SMBus, it provides a much broader degree of standardization and allows the use of standard libaries and drivers for many processors.  it also has the advantage of providing discovery features to allow the system to "learn" about a connected device by reading values out of it that provide details like what data formats it uses, what features and commands it supports.

Since all three use the same 2-wire, open drain interface, most processor's standard I2C peripheral can be used to communicate with I2C, SMBus or PMBus devices.

SPI or Serial Peripheral Interface, is a "standard" (with a lot of variants) 2-wire, push-pull bidirectional data base.  As a push-pull interface, it generally does not support multi-drops, but can with a separate "chip select" line that enables only the 1 device that is being addressed at a time.  It has the advantage of speed over  the open drain serial buses, commonly operating in the 5-20MHz bus speeds, and frequently with longer transactions, generally 16 or 32 bits per "frame"  The disadvantage is it generally requires a lot more write routing, a lot more power, and is far less standardized than even I2C, requiring custom configuration firmware on the system side.  SPI interfaces also tend to suffer from fixed transaction "frames" that can limit the data transfer.

PMBus includes an open standard "AVS Bus" (officially called PMBus Part III) that adds the same kinds of standardization that PMBus added to SMBus on top of a high-speed SPI based interface specifically for point to point to point communications between a power device requiring adaptive voltage scaling, and it's power supply.