TPS65219: AM6442 with TPS6512904 on PIN28 (MODE/RESET) design.

Hi,

Thank You for using E2E. I'll respond to the question #3 here and will reassign the ticket to the Sitara processor team so they can comment on the first and second questions.

Bo-Wei Lin said:

3. When MODE/RESET receives the LOW signal, a Warm reset will be performed according to the settings of TPS6521904. That means that the nRSTOUT of TPS6521904 will also be reset to achieve system cleanup RESET?

The MODE/RESET pin of the TPS6521904 is configured as "WARM RESET". This configuration resets the register settings to the default values without turning-OFF any of the PMIC rails or nRSTOUT. 

Thanks,

Brenda

thank you for your reply

So assuming I want to use the nRSTOUT of the TPS6521904 to reset the AM6442 seems impossible! right?

Then I would like to extend my inquiry. In the MODE/RESET of TPS6521904, how many seconds of LOW need to be maintained before a reset is triggered?

Hi,

The deglitch of the MODE/RESET pin and all other digital pins can be found in the data sheet. For the MODE/RESET, it would be parameter "tDEGL_RESET" and its 120us (Typical).  

Thanks,

Brenda

Hello Bo-Wei Lin

Bo-Wei Lin said:

1. Do you need to give RESETSTATz of AM6442 a trigger source? Can the trigger source be the GPIO of AM6442? There is no other signal source in my design that can control RESETSTATz.

The  RESETSTATz is main domain warm reset status output. This can be controlled by any of the reset inputs - Cold or warm.

Bo-Wei Lin said:

2. Can I use general GPIO as input through AND gate and RESETSTATz, and then when my system needs to be reset, I can immediately reset the system through GPIO control?

For resetting the SoC you could use the warm reset inputs or perform warm reset by software.

Please read the TRM for more information on Reset.

We have a FAQ that lists key collaterals with links

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1272574/faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design-usb2-0-interface

Regards,

Sreenivasa

TKS,

The current product design does not have additional hardware to trigger any reset, whether it is MCU or MAIN
1. I connected the Cold reset of the MCU to the TPS6521904 as above, but when the TPS6521904 is reset, the corresponding nRSTOUT pin will not be reset synchronously.

2. I currently plan to use the AM6442’s own GPIO via a pull-up resistor to control the Warm reset of the MCU and MAIN. Is this okay?

Thank you for your reply.

I would like to ask if GPO2 will be reset when TPS6521904 is reset? Or will it still remain in the High state?

Hello Bo-Wei Lin

Thank you .

Bo-Wei Lin said:

I connected the Cold reset of the MCU to the TPS6521904 as above, but when the TPS6521904 is reset, the corresponding nRSTOUT pin will not be reset synchronously.

Please help me understand what you mean by synchronously. Please refer to the data sheet and PMIC configuration manual.

Bo-Wei Lin said:

2. I currently plan to use the AM6442’s own GPIO via a pull-up resistor to control the Warm reset of the MCU and MAIN. Is this okay?

Could you not use some internal reset.

Did you mean MCU or MAIN domain? 

Can you please write a simple diagram?

Regards,

Sreenivasa

Hello Bo-Wei Lin

Pease refer to the below document and the listed diagrams.

https://www.ti.com/lit/ug/slvucl1a/slvucl1a.pdf

Figure 2-1. TPS6521904 Power-Up Sequence

Figure 2-2. TPS6521904 Power-Down Sequence

Figure 2-3. TPS6521904 Example Power Block Diagram

I will request the PMCI to add additional information as required.

Regards,

Sreenivasa

Thank you very much for your reply. I have sorted out the schematic diagram of my AM6442x with TPS65219. If there is anything unclear, please reply.

The following questions
1. Suppose I use the method shown in the diagram to control RESET_REQz. Is it possible? The risk is that when I give the low signal AM6442x to perform warm rest, this GPIO will be in the UNKNOW state. Can the low state time comply with 1.2us? ?

2. According to all my components, the longest reset time key is 120us. Continuing the above, can I have a way to ensure that RESET_REQz can maintain at least 120us? When my AM6442x has triggered warm rest, my idea is to pull low when the signal is pulled When low, the level can be ensured to avoid the UNKNOW state during initialization, and then the firmware keeps this GPIO in the low state until the time matches and then pulls up.

3. When TPS6521904 warms reset, does GPO2 always remain High?

TKS.

Hello Bo-Wei Lin

Thank you.

Bo-Wei Lin said:

1. Suppose I use the method shown in the diagram to control RESET_REQz. Is it possible? The risk is that when I give the low signal AM6442x to perform warm rest, this GPIO will be in the UNKNOW state. Can the low state time comply with 1.2us? ?

The PORZ_OUt is cold reset output and this is the power supply On/OFF. A 1.2 us control may not be feasible.

Bo-Wei Lin said:

2. According to all my components, the longest reset time key is 120us. Continuing the above, can I have a way to ensure that RESET_REQz can maintain at least 120us? When my AM6442x has triggered warm rest, my idea is to pull low when the signal is pulled When low, the level can be ensured to avoid the UNKNOW state during initialization, and then the firmware keeps this GPIO in the low state until the time matches and then pulls up.

Any IO control on the SoC can be performed only after the SoC boots.

The 120 us timing may not be feasible.

Bo-Wei Lin said:

3. When TPS6521904 warms reset, does GPO2 always remain High?

Helo me understand what you mean by warm reset for the PMIC.

Regards,

Sreenivasa

Thank you for your very prompt reply
1. Yes, but I will be doing control in the PHY part, so there is no special problem. The main thing is, is this kind of control loop okay?

2. According to your reply, I think my idea is OK. Before SoC boot, I use hardware pull-down to maintain the status, and re-firmware control of these GPIOs. After SoC boot, the output continues to be low until the time is up. Transition to High

3. The Warm reset of the PMIC is set by TPS6521904. According to the following instructions in the above reply specification, The MODE/RESET pin of the TPS6521904 is configured as "WARM RESET". This configuration resets the register settings to the default values ​​without turning -OFF any of the PMIC rails or nRSTOUT. But I need to determine if the GPO is also one of them.

Bo-Wei Lin said:

1. Yes, but I will be doing control in the PHY part, so there is no special problem. The main thing is, is this kind of control loop okay?

Not sure i understand. fully.

Below is the cold reset timing?

and warm reset timing.

1.2 us would be the min time.

Let me check regarding the PMIC warm reset.

Regards,

Sreenivasa

Thank you for your reply.

The main loop is that I use the GPIO of the AM64x itself to control the RESET_REQz part. Can this control method operate normally?

Regards,

LIN

Yes, we later discovered that it can be controlled by software. From this point of view, my doubts can be completely solved. As for the circuit part, it was originally an idea when I didn’t know that software could be controlled. Of course, I wanted to understand this out of the spirit of application. Is it appropriate to use?

Thank you very much for your patience in replying to the discussion!

Hello Bo-Wei Lin

Thank you and Happy to support.

Glad you have been able to make the required decision.

Is this a new project that you are starting?

Regards,

Sreenivasa

Hello Bo-Wei Lin

We have comprehensive design collaterals and FAQs to support custom design.

I have the below 2 FAQs that provides links to the collaterals for your reference.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1185502/faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design-collaterals-to-get-started

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1274160/faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---faqs-related-to-processor-collaterals-functioning-peripherals-interface-and-evm-starter-kit

Regards,

Sreenivasa