Other Parts Discussed in Thread: AM6412, AM6422, , AM2434, TPS65220, TPS65219, TMDS64EVM, SK-AM64B, AM6411, AM6421, AM6441
Hi TI Experts,
Can you provide a List of collaterals that can be referred when starting a custom board hardware design.
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Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
Device Selection and features
Product Pages
https://www.ti.com/product/AM6442
https://www.ti.com/product/AM6441
https://www.ti.com/product/AM6422
https://www.ti.com/product/AM6421
https://www.ti.com/product/AM6412
https://www.ti.com/product/AM6411
Datasheet
AM64x Sitara Processors datasheet
https://www.ti.com/lit/pdf/sprsp56
Silicon Errata
AM64x/AM243x Processor Silicon Revision 1.0, 2.0
https://www.ti.com/lit/pdf/sprz457
Technical Reference Manual
AM64x /AM243x Processors Technical Reference Manual
https://www.ti.com/lit/pdf/spruim2
Custom Board design:
Hardware Design Considerations
Hardware Design Considerations for Custom Board Using AM6442 , AM6422 , AM6412 and AM2434 Processors
https://www.ti.com/lit/pdf/sprad67
Schematic Design and Review Checklist
AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist
https://www.ti.com/lit/pdf/spracu5
Power Consumption
AM64x Maximum Current Ratings
https://www.ti.com/tool/download/SPRR451
AM64x/AM243x Power Estimation Tool
https://www.ti.com/lit/pdf/spracw6
SoC power solutions Application notes:
Powering the AM64x with the TPS65220 or TPS65219 PMIC
https://www.ti.com/lit/pdf/slvafe9
Evaluation - EVM
TMDS64EVM Design Package Folder and Files List
www.ti.com/.../TMDS64EVM
https://www.ti.com/lit/pdf/sprt782
TMDS64EVM Design File Package
https://www.ti.com/lit/zip/sprr462
SK-AM64B Design Package Folder and Files List
www.ti.com/.../SK-AM64B
https://www.ti.com/lit/pdf/sprt783
SK-AM64B Design File Package
https://www.ti.com/lit/zip/sprr460
Add-on cards
Schematics (Reference) for RMII interface
Note: We did functionally validate the common clock configuration. No other clocking options were tested.
Ethernet PHY daughter card
https://www.ti.com/tool/DP83867-EVM-AM
https://www.ti.com/tool/DP83826-EVM-AM2
https://www.ti.com/tool/TIDA-00928
GPMC NAND Expansion Card
HSE NAND EXP BOARD + BREAKOUT BOARD.zip
here seems to be a muxed GPMC interface implemented.
https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/TMDXICE3359_SCH.pdf
PinMux
CAD symbols
Cad symbol specific to the selected device can be chosen from the device product page. Refer below example:
https://www.ti.com/product/AM6442#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM6442#order-quality
https://www.ti.com/product/AM6441#order-quality
https://www.ti.com/product/AM6422#order-quality
https://www.ti.com/product/AM6421#order-quality
https://www.ti.com/product/AM6412#order-quality
https://www.ti.com/product/AM6411#order-quality
Package pad diameter and substrate pad dimension
AM64x -> ALV pkg : ball diameter 0.5mm : substrate pad 0.45mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.
Lead finish/Ball material
SnAgCu
DDR Board Design and Layout Guidelines
AM64x\AM243x DDR Board Design and Layout Guidelines
https://www.ti.com/lit/pdf/spracu1
Escape Routing for PCB Design
AM64x and AM243x BGA Escape Routing
https://www.ti.com/lit/pdf/spruiy5
Design Simulation files
https://www.ti.com/product/AM6442#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model, power-estimation tool (PET) and Maximum Current Ratings.
IBIS model
https://www.ti.com/lit/zip/sprm730
Thermal model attached in case the thread is not accessible.0268.sprm773a.zip
(23) AM6442: Ansys Compatible Thermal Model - Processors forum - Processors - TI E2E support forums
Layer Stackup
TMDS64EVM_PROC101_Stack_up.pdf
AM64x PDN Target impedance values:
Impedance target values for VDD_CORE on AM64x
Low freq (< 1MHz): 15 mOhm
Mid freq (1 < 20MHz): 35 mOhm
High freq (20 < 50 MHz): 35 mOhm
This is valid for either of the core voltage voltages (0.75V, 0.85V). We do not provide target impedance values for other rails on AM64x.
For frequencies above 50 MHz the board decoupling caps do not play a critical role. SoC and Package decaps (if any) will be dominant beyond 50 MHz
Note:
We do not include Buck output inductance in PDN simulations.
For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
AM62x, AM62Lx DDR Board Design and Layout Guidelines
https://www.ti.com/lit/pdf/sprad06
Refer to the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
The DDR design guidelines outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.
Power Distribution Networks: Implementation and Analysis
Sitara Processor Power Distribution Networks: Implementation and Analysis
https://www.ti.com/lit/pdf/sprac76
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/pdf/spraar7
https://www.ti.com/lit/pdf/spracn9
https://www.ti.com/lit/pdf/sprabi1
Technical Documents
Collaterals and application notes
https://www.ti.com/product/AM6442#tech-docs
Technical Support
AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board design - FAQs
Previous E2E threads - Keywords AM64x, AM644X, AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
Starting a new thread
Useful links
Sitara family of processors FAQ master list
Other FAQs
Notes
Regards,
Sreenivasa
Hi Board designers,
Configuring Hysteresis
Data sheet
6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-35. GPIO0 Signal Descriptions
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10.2 MCU Domain
Table 6-37. MCU_GPIO0 Signal Descriptions
TRM
5.1.1.3.1.1 Pad Configuration Registers
The pad configuration registers are used to configure most of the device pads. Each pad configuration register
(PADMMR_PADCONFIG0 to PADMMR_PADCONFIG181) is assotiated only with one pad and has bits as
described in Table 5-4.
Regards,
Sreenivasa
Hi Board designers,
Inputs regarding board simulation
Refer below for the AC Impedance plot for VDD_CORE.
The board has undergone full split lot validation with this combination of filtering/decaps.
Regards,
Sreenivasa
Hi Board designers,
Inputs regarding Package shelf life
Please refer below links
https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html
https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html
https://www.ti.com/support-quality/reliability/reliability-home.html
https://www.ti.com/lit/an/spraby1a/spraby1a.pdf
https://www.ti.com/lit/pdf/snoa550
https://www.ti.com/lit/an/slva840/slva840.pdf
/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf
Regards,
Sreenivasa