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LM5157: Request for EVM Gerber Files

Part Number: LM5157

Hello,

I would like to request to get a copy of the Gerber files for the LM5157EVM-SEPIC Module

Thanks,

Deniel

  • Hi Deniel,

    Thanks for reaching out! I've attached the Altium files related to the EVM to this post.
    Do you have access to Altium or would you need help generating the Gerber files?

    Thank you and best regards,
    Bryan 


    LM5157EVM-SEPIC.zip

  • Hello Bryan,

    Thanks for the Altium Files. I am using Kicad.

    I do need help generating the Gerber Files.

    Thanks,

    Deniel

  • Hello Deniel,

    You're very welcome. Please have some patience, I will get back to you tomorrow with the relevant Gerber files.

    Thank you and best regards,
    Bryan

  • Hi Deniel,

    I've generated the Gerber files, let me know if you have further questions.

    Best regards,
    Bryan

    Gerber_LM5157EVM_SEPIC.zip

  • Hi Bryan,

    Thanks for the Gerber Files.

    I have some additional questions about the LM5157 SEPIC EVM. Let me know if I should open a new question for this topic

    1. Why does the EVM have qty: 5 10uF Output Capacitors? Is the total capacitance 50uF needed to get a specific ripple voltage?

    2. Why Is C14 and C15 (connected to another ground plane location) not together with C12,13,16?

    3. Similar question, Why is not C7 (connected to another ground plane location) not together with C1 and C2?

    3. What is the purpose of C10 and C11? Why is the reason for its location in the EVM layout

    4. In the LM5157 Calculator for SEPIC, our calculated minimum output capacitor is 50uF. Can we use a single 50uF Capacitor (ceramic or electrolytic) or do we need to split them off as well like the EVM?

    Thanks,

    Deniel

  • Hi Deniel,

    You're welcome. I'll answer your questions in this thread, you don't need to make a new one.

    Q1: These ceramic capacitances are in parallel because in this way you also make the ESR smaller, as resistors in parallel cause a smaller effective resistance, you also decrease their stray inductance in this way.
    Q2: It is always good practice to use symmetry in PCB routing, for better EMI behavior. Furthermore the electrolytic capacitor C9 is located on the other side of the board, in parallel to C12,C13 and C16.
    Q3: Like in Q2, using symmetry and optimizing the fields by connecting the Vin pad to ground in this way.
    Q4: It is often useful to add smaller capacitances in parallel to the bigger ones. If you take a look at the classical differential equation of capacitors (I=C*dU/dt) you see that smaller capacitances can respond more quickly to high-frequency signals.
    Q5: Definitely use the type of specified capacitors like the ones used in the EVM. The capacitance value of electrolytic capacitors greatly varies across the frequency range and they have less than optimal ESR and self-resonant frequencies.

    (You used the #3 two times for your questions, please don't be confused because I have 5 answers)

    Thank you and best regards,
    Bryan

  • Hi Bryan,

    Thanks for your response and clarification 

    I have some follow up questions on the output ceramic capacitors 

    In the EVM, All the ceramic capacitors are in the top layer and are 1210 in size, 50V Rated

    As I mentioned, our calculated minimum output capacitor is 50uF.

    Our output voltage is 12V with max output current of 1.5A

    In order to save space in our layout and have more parallel capacitors, can we follow the EVM layout by

    Option 1

    1. having another VOUT plane in the bottom layer 

    2. Placing four 0805 10uF 35V rated ceramic capacitors on the top layer that are have symmetrical setup like the EVM

    3. Placing four more 0805 10uF 35V rated ceramic capacitors on the bottom layer similar to the Top layer setup

    The total capacitance is now 80uF

    Option 2

    1. Placing four 1206 22uF 25V rated ceramic capacitors on the top layer that are have symmetrical setup like the EVM

    2.  Possibly Placing 2-4 more 1206 22uF 25V rated ceramic capacitors on the bottom layer with an additional VOUT bottom layer plane

    The total capacitance is now 88-176uF

    Will there be issues implementing any of these setup? 

    Thanks,

    Deniel

  • Hi Deniel,

    You're welcome, thanks for reaching out.

    I think it be beneficial if you could share the filled out Quickstart Calculator excel file (that you used to calculate the 50uF) with me. In this way I know more about your required parameters, enabling me to better understand your ideas regarding PCB placement.

    Thank you and best regards,
    Bryan

  • Hello Bryan,

    I have attached the filled out quick start calculator excel file for our LM5157 Design

    We selected the voltage ripple of 200mv (<2% of 12V output)

    Thanks,

    Deniel

    LM5157-58_Excel_Quickstart_Calculator_for_SEPIC_filled_up.xlsx

  • Hi Deniel,

    Thank you, give me some time to look at your schematic with the new information.

    Best regards,
    Bryan

  • Hi Deniel,

    thanks for sharing the quickstart calculator. The setting in this calculator looks good.

    Regarding the two options you asked above. Both are basically OK but you need to check the parameter of the used capacitors and check the value of the DC bias of the output caps. The capacitance of ceramic capacitor can be reduced to a value of 20-60% of the give value when operated in DC mode but depends on the capacitor.

    This you can only see for the parameter - see here for some good technical explanations:

    Does the capacitance change when a DC voltage is applied to ceramic capacitors? Are there any points to be aware of regarding changes in the capacitance? | Capacitors FAQ | Murata Manufacturing Co., Ltd.

    The value given in the calculator is the effective capacitance you need, so case of reluctance of 50% due to DC bias you need to add twice the value.

    Best regards,

     Stefan