• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 110 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65919-Q1: Analyze the result at a special scene

Jack Li
Intellectual 1540 points
Part Number: TPS65919-Q1

Hi team,

Here is my customer device solution background: The platform is TDA2EGBHQCBDQ1, and the PMIC is O919A14CTRGZRQ1 (TPS65919). 
There is a scene during operation: When the PMIC's VCCA and VCC_SENSE are turning off and the voltage is 0V, but LDO12_IN still maintains 3.3V input. 
Based on this scene, the customer have the following questions, 
     Question 1: What will happen when LDO12_IN is supplied before SMPS1/2/3 power up?
     Question 2: In this scene, is there any risk of backward current inside the PMIC?
     Question 3: They wonder whether LDO1/2 can output normally at this time, or disable and no output?
     Question 4: In this scene, will it cause PMIC power up abnormally?
Here is their schematic:
 
      Question 5: If the LDO1/2 can output normally, what will change for the power-on sequence?
 
Looking forward to your reply, thanks in advance!

Best Regards!
Jack


  • 0
    TI__Mastermind 38791 points

    Hi Brian,

      Listed below are the direct answers:

    1. It's not designed for the use case; power up/down sequence will be void. 

    2. Yes.

    3. Not sure; no test was done.

    4. Not sure; no test was done.

    5. Power up/down sequence will be void. 

    Thanks!

    Phil