Hi team,
Could you please help me understand why operating at higher input voltage, the bootstrap voltage would drop below UVLO?
And Why after high-side current limit is triggered and then the low-side current limit is triggered?
Why the output voltage drops as below?
Hi Fhoude,
I certainly will search the key word in E2E before I create a post. Please understand I start a post because I haven't got a clear answer looking at previous posts.
1. I want to understand why operating at higher input voltage will trigger bootstrap UVLO. From my understanding, BST UVLO usually happens at large duty cycle like dropout mode because the low-side FET on time is too short, the bootstrap cap doesn't have enough time to be charged. What is the criteria for higher input voltage?
2. Why higher high-side mosfet Rdson will trip high side current limit? Is it because we use a comparator to monitor the voltage of Rdson* current to decide the limit?
3. Why the Vout will decrease like below waveform and what is toc?
Thanks for your support in advance!
Hello Iris,
1) The higher input voltage doesn't directly affect BST UV condition. It does affect triggering the LS ILIM because the LS fet is turned on to charge the CBST, but at the same time it discharges the output capacitance too. At higher input voltages the output capacitor is charged to higher voltages when in open circuit condition. When you go to charge the CBST then the current going through the LS FET is large and can trip the LS ILIM setpoint thus you get a current limit event.
2) The internal circuitry looks at the Vds of the HS FET compared to a reference Vds to determine if the device hits current limit. The circuitry assumes the HS FET is fully enhanced, but at lower boot strap voltages the HS FET can be only partially enhanced and thus is closer to the linear region of the HS FET. The when that Vds is compared to the reference Vds it will look like a over current limit event, despite the current through the FET is in fact not hitting the threshold that constitutes a HS ILIM event. That is due to how well the FET is enhanced, which is a function of the voltage across the HS gate driver which is powered by CBST. We want to avoid being close to the BST UV condition by either changing the CBST, PWM off time, and PWM frequency (or PWM period). The stair step waveform you see above is due to this event and it constitutes the CASE 3 we outline in the datasheet.
3) Vout stair steps because the LS FET is turned on during a soft start (which happens whenever there is either a HS or LS ILIM event, which discharged COMP capacitor) event and it charges up the CBST. Because it is a prolonged period of time, the output voltage is discharged until the current hits the LS ILIM setpoint (~1.5A - negative direction). Once LS FET is turned off the channel is disabled for ~3.6ms (TOC), thus Cout stays charged at the level until the device retries a startup after 3.6ms. Then the output is discharged again until it hit LS ILIM setpoint.
