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TPS38-Q1: Problems when testing 24VDD instantaneous power failure

Satoshi
Guru 19565 points
Part Number: TPS38-Q1

Customer are conducting a 24V momentary power failure test on the TPS38A010122 circuit, and the conditions and phenomena are as follows.

・VDD: 24V (ch4, Red)

・SENSE1/2: 8.13V divided from 24VDD

・CTR1/2: 0.1μF

・CTS1/2：Open

・/RESET1: Pull up from 24VDD (ch1, Yellow)

・/RESET2: Pull up from 3.3V of another system (ch2, Green)

As shown in the waveform, when 24VDD is momentarily dropped, either reset output drops and then rises again.

(The waveform is /RESET1, but sometimes occurs at /RESET2)

Incidentally, the same result is obtained even if the momentary power failure time is 50μs (> tcs).

   

There are three questions below.

① Is there a way to avoid this behavior where it drops for a moment and then rises again?

②What is the cause of this behavior?

    I am guessing that wraparound is occurring from one side of the Reset output, is this correct?

③Is it not allowed to use VDD and SENSE1/2 on the same power line?

Best regards,

Satoshi

  • 0
    TI__Expert 3580 points

    Hi Satoshi, 

    Thanks for your question. I want you to know that I'm looking into the matter. Can you please provide the following clarification so we may better assist you?

    - The resistor values (voltage divider at the SENSE1 and SENSE2 pin), and your pull resistor values?  

    - Slew rate for VDD (24V (ch4, Red))? 

    Regards,

    Sila Atalar 

  • 0 in reply to Sila Atalar
    Guru 19565 points

    Hi Sila

    Thank you for reply,

    Please refer about resistor value below;

    ・Voltage divider at the SENSE1 and SENSE2 pin: R_top: 22kΩ, R_bottom: 2.4kΩ

    ・Pullup for /RESET1 (24V): 10kΩ

    ・Pullup for /RESET2 : The output side was separated into two lines, 3.3V/4.7kΩ and 1.8V/4.7kΩ.

    I will confirm slew rate and feedback to you.

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    Guru 19565 points

    Hi Sila,

    I confirmed to customer, but there is no slew rate condition because it is externally dependent.

    As a countermeasure, I'm considering whether it is possible to add capacitors to both CTSs to create a period of about 1 ms in which glitches are ignored.

    Is it possible to solve this problem using this method?

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    TI__Expert 3580 points

    Hi Satoshi, 

    Yes, Adding CTS capacitor is also my suggestion. I just wanted to check if their configuration is correct. Please let me know if they still have the same problem  after adding the capacitor. 

    Best Regards,

    Sila Atalar