UCC2818A-Q1: Multiplier Block Power Limit

Hello Akshay,

Thank you for your question concerning the power-limit parameter in the UCC2818A-Q1 datasheet.

I had seen this parameter years ago and wondered how to use it, too, but never had a chance to follow up. 
Your question forced me to investigate further.  

Basically, this parameter can be used to scale controller designs from one PFC power level to another by using resistor ratios to reduce the math involved. 
But without supporting equations and details on how to apply it, this parameter is basically useless and you can ignore it. 
PFC designs are routinely done without it. 

First of all, it is not a limitation of the multiplier-block internal dissipation, but a scaling-factor for the power limit of the PFC design.   
For the given test conditions (Iac = 150uA, Vff = 1.4V, VAOUT = 5V), the product of Imout x Vff = 420uW.

In the UCC2818A-Q1, Imout cannot exceed 2xIac, and when Iac = 150uA, Imout </= 300uA max.  For Vff = 1.4V, 300uA x 1.4V = 420uW.
The value is negative because Imout current flows OUT of the MOUT pin, which is defined as negative (current flowing into a pin is positive). 
So it is really -300uA x 1.4V = -420uW.   Let's call this parameter kPL (a power-limit factor).

In the normal design procedure, PFC power limit is determined by other design equations and the -420uW parameter is not used, so it is a superfluous specification.
But the other equations can be used to speculate on its original intention. 

With UCC2818A-Q1, the PFC is designed to limit the maximum input power (Pin(limit)) at the lowest RMS input voltage and maximum output load.  In steady-state operation, Pin(limit) cannot be exceeded no matter how much overload is placed on the output.  (Note: this limit can be briefly exceeded during transient conditions.)

With voltage feed-forward (VFF), the voltage-loop error-amplifier output (offset by +1V) is directly proportional to output power so VAOUT = 5V represents 100% Pout. 

In design, the VFF pin voltage is targeted to be 1.4V at the minimum Vrms input voltage (85Vrms, for example) set by Rvff in equation (11).   Riac is previously determined in the second-to-last paragraph on page 13 of the UCC2818A-Q1 datasheet.  That puts Iac at about 150uA at 85Vrms input.

Under these conditions at full power, Imout = 150uA * (5V - 1V) / (1.4)^2 = 300uA per equation (10).  
For the design example of 100% Pout = 250W and assuming >90% efficiency and PF > 0.99, Iac input = 278W/85V/0.99 = 3.30Arms, so Iin_pk = 4.672Apk.
This is the average inductor current at the peak of low-line at full power (ignoring ripple current).
The current-sense resistor Rs scales this peak to a voltage Vrsense.  Imout develops a matching voltage through Rmout, and the current-loop acts to shape the average inductor current to follow the MOUT reference current over the line cycle.  At low-line peak, Iin_pk*Rs = Imout*Rmout, per equation (16).  

Therefore, Imout(max) = (Rs/Rmout)*Iin_pk, and Iin_pk = ((Poutmax/eff)/Vrmsmin)*1.414.
And Vff = 1.4V at Vin = 85Vrms, based on 1.4V = 85Vrms*(0.9*Rvff)/(2*Riac) (rearrangement of equation (11)).

Since kPL = Imout*Vff, substitution shows kPL = [(Rs/Rmout)*((Poutmax/eff)/Vrmsmin)*1.414] * [Vrmsmin*(0.9/2)*Rvff/Riac)].
Solving for Pin limit gives:  (Pout/eff) = kPL * (Rmout/Rs) * (Riac/Rvff) * (1.414/0.9).
Plugging in values from the datasheet design example,  Pin (limit) = 420uW * (4000/0.25) * (766k/30k) * 1.57 = 269W input limit for a 250W nominal PFC design. 

So using the Pin Limit equation just above, with kPL = 420uW, one may quickly scale the (Rmout/Rs) and (Riac/Rvff) ratios to other power levels and input voltage ranges, provided that one design is already done.  
However... since different power levels and voltages will require different inductor, capacitor, and semiconductor ratings, the kPL factor is of very limited usefulness and for that reason, I think it was neglected of supporting design equations.  Personally, I think it should be removed from the Electrical Characteristics table simply to avoid confusion. 

Regards,
Ulrich 

Hello Akshay, 

I found that there is a little bit more to the story. 

Figure 12 (on page 20 of the UCC2818A-Q1 datasheet) is a graph of (Vff x Imout) and the 420uW parameter in the EC table represents one data point on the upper-most curve.

Basically, this curve shows that the power limit stays relatively constant for any given VAOUT level (output power level) as Vff varies between minimum and maximum (low-line to high-line).  Constant power limit is possible because as Iac and Vff go up (as Vrms input goes up) the Imout current goes down to compensate due to Vff^2 in the denominator of  equation (10). 

Lower values of VAOUT result in lower power limits.  So if VAOUT is clamped to a lower voltage by an external circuit (for some special application), the maximum power limit is also lowered. 

Other than indicating a tested point on the VAOUT = 5V curve, I don't see any other use for the "kPL" factor. 

Regards,
Ulrich