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TPS2595EVM: TPS2595EVM

JAEWON CHUNG
Prodigy 20 points
Part Number: TPS2595EVM

As for input voltage for VEN of TPS259541DSGR, the datasheet says as below;

"For supply voltages greater than 6V, it is recommended to use an appropriate resistor divider

between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits."

The maximum voltage for enable pin is specified as 6V.

Below schematic is from TPS2595EVM manual.

  

Q1) When using 12V as VIN, the enable pin voltage is likely to exceed the recommended operating range, i.e, 0V to 6V because

only 1M ohm pull-up resistor is connected to VIN. Is it working fine under 12V input condition?

Q2) As to TPS259541, is there a way to disable undervoltage lockout feature?

Your kind advisement would be thankful.

Jaewon.

  • 0
    TI__Genius 14755 points

    Hi Jaewon,

    Q1) When using 12V as VIN, the enable pin voltage is likely to exceed the recommended operating range, i.e, 0V to 6V because only 1M ohm pull-up resistor is connected to VIN. Is it working fine under 12V input condition?

    A1) Yes, please do not apply more than 6V at the enable pin. The threshold at the enable pin is even lower (around 1.2V) so any voltage greater than this and less than recommended maximum is fine. What I suggest is you can add a resistor across the J5 jumper pins to create a resistor divider and control the voltage at the enable pin. I know this is not very elegant solution but it works here. 

    Q2) As to TPS259541, is there a way to disable undervoltage lockout feature?

    A2) You can use an external power supply after removing the pull up resistor R17 and disconnecting the J5 jumper.

    Please reply here if any further query or click resolved if no more questions. 

    Best Regards,
    Arush

  • 0
    Prodigy 20 points

    A1-R) According to what you remarked, it looks the schematic needs to be revised.

    A2-R) It means the EN/UVLO pin is left floating for disabling undervoltage lockout. BTW, the datasheet says "Do not leave floating"

    A little bit confusing. Could you kindly clarify it?

    (Datasheet revision: SLVSE57C –JUNE 2017–REVISED APRIL 2018)

    Regards/Jaewon

  • +1 in reply to JAEWON CHUNG
    TI__Genius 14755 points

    Hi Jaewon,

    1. Yes, I am aware that U1 and U3 have this issue (En signa when testing for more than 6V input voltage) but EVMs cannot be modified as they are already made.

    2. No, I didn't mean to keep it floating. I am attaching a snip to explain what I meant.

    Please reply here if this is still not clear. You can use any external voltage greater than 1.2V to disable the UVLO feature. 

    Best Regards,
    Arush