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UCC5870-Q1: PWM_COMP_CHK_FAULT asserts during rapid motor accelerations

Part Number: UCC5870-Q1

INT_COMM_PRI_FAULT and CLK_MON_PRI_FAULT bits are also set.

Status1 register: 0x80E0

Status2 register: 0x40A6

Bit status indicates there is a problem with communication between the primary and secondary sides of the chip. This fault occurs when we're commanding rapid accelerations of the motor. Why would this fault occur during rapid accelerations? How can we correct this?  Thank you in advance for any information/advice you can provide. 

  • Hi Tom,

    Thanks for reaching out.

    Based on the symptoms you describe, I see two possibilities. These faults all can indicate corruption on the internal communication lanes. Because of this, all appearing at once typically indicate:

    1. Loss of VCC2, typically a very fast loss. This can be confirmed or eliminated by  probing VCC2 during the failure.

    2. Excessive radiated noise, or excessive noise from GND1-GND2 at high frequencies, >350MHz, is present in the system during this rapid acceleration scenario. Typically this is addressed by:

    • Optimizing the gate driver layout and bypass capacitor placement
    • Improving high current switching paths
    • Adding shields between high current paths (Bus bars, DC link capacitor, Switch node) and the gate driver
    • These faults can also be ignored by setting them the FAULT_P bits associated with them to do not report with minimal effect on the system. The risk is that some data, in particular ADC results or fault information, is lost.

    My recommended troubleshooting steps are:

    1. Probe VCC2 during the failure and check for undervoltage
    2. Probe from GND1-GND2 with a 800MHz-1GHz probe and check for high frequency ringing
    3. Try adding copper tape or a copper shield between the gate driver and power stage to decouple noise.
    4. Review layout for any issues. TI can help with this if you share your schematic and layout.

    Finally, I would recommend our newest gate driver, UCC5880, with increased CMTI ratings and a corresponding increase in transient immunity. 

    Regards,

    Daniel Norwood

  • Hi Daniel, thanks for both the speed and completeness of your reply. The support in this forum is awesome!   Just a quick clarification of the description I sent before;  This error consistently occurs (in 8 trials) on the same one phase (V high) in our design and not on the other motor phases/gate drivers. Note sure if the additional data changes any of the recommendations above, but I did want to share it. 

  • Hi Tom,

    That is a good piece of information! It means we can focus specifically on that driver.

    Could you review the entire inverter stack up, is this gate driver closer to bus bars or the DC link capacitor than other drivers? Are there any layout differences? This isn't really a change to my recommendations, just the ability to focus!

    Regards,

    Daniel