UCC28070: UCC28070

Hello Venkatesh, 

As you noted above, frequency dithering is an optional feature and is not required for correct PFC operation.
In fact, I recommend to keep dithering disabled during the entire time of prototype board debug and evaluation, until the board performs satisfactorily to your expectations. 
Once an bench-mark conducted EMI scan is recorded, then dithering can be enabled to determine the improvement and see if it can reduce EMI further by adjusting the dithering parameters empirically. 

The choice of dithering magnitude and dithering rate depend, in part, on the nominal fixed frequency of the PFC.

Basically, conducted-EMI noise is measured by scanning the output of a LISN with a spectrum analyzer that uses a 9kHz "window" to detect the frequency content of the AC line. 
This window is swept from 150kHz to 30MHz and signals of interest are centered withing the window to measure their amplitudes. 
Given that the window provides a view of frequencies from -4.5kHz to +4.5kHz from the center frequency, it is advantageous to move the PFC switching frequency out of this viewing window for some period of time to reduce the average and quasi-peak signal levels detected within the window. 

I suggest that the harmonic of the switching frequency that first appears closest to the 150kHz conducted-EMI boundary should be used to determine the dithering magnitude.
This harmonic (whether 1st (fundamental), 2nd, 3rd,... etc.) should be swept by around +/-10kHz, up to +/-10%, from its nominal center. 
For example, if fPWM is programmed for 200kHz, then the fundamental is already within the conducted EMI band and dithering should be set for +/-10kHz to +/-20kHz in magnitude.    Conversely, if fPWM is programmed for 40kHz, then the 4th harmonic 160kHz falls within the conducted EMI band and dithering should be set for +/-10kHz to +/-20kHz in magnitude of the 4th harmonic.  This translates to +/-2.5kHz to +/-5kHz dithering of the fundamental frequency. 

I advise against excessively wide dithering because the inductor peak currents may be come excessively high when dithering is at the lowest frequency.   

The dither rate is how fast (or how often) the switching frequency changes from -% up to +% back to -%.  
Dithering too slowly will expose the harmonic within the 9kHz window for too long and no significant reduction in EMI energy will be detected.
Dithering too fast may shift the PWM frequency up and down faster than the current loop can keep up with and can lead to higher distortion (THDi) or even instability. 
Dithering "just right" can optimize the reduction of EMI signature, but determining what rate is just right is an empirical process.  
I suggest to start with a rate of 1kHz which means that fPWM moves from lowest to highest to lowest once every 1ms.  This should be within the bandwidth of most current amplifier designs.  The PWM frequency or its harmonic will stay out of the 9kHz detection window for a significant part of the 1ms.  The magnitude of dithering will determine what percentage of the 1ms rate has fPWM outside of the window. 

Trial and error adjustment of rate and magnitude can optimize the reduction of conducted-EMI noise. 
As I mentioned above, don't enable dithering until after all other operations of the PFC meet your performance goals.  

Regards,
Ulrich