Other Parts Discussed in Thread: TPS62A06
Hi,
Does TPS62A06A have Verilog model for simulation?
Is it can provide to customer?
Thank you!
Jeff
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Hi Jeff,
No, we do not have a Verilog model for this device.
Any available models would be here: https://www.ti.com/product/TPS62A06A#design-development
Chris
Hi Chris,
I can find TP62A01 simulation model on website, but can't TPS62A06 simulation model on website.
Does TPS62A06 have this file? thank you!
Jeff
Hi Jeff,
No, there is not a model for TPS62A06.
What do you need to model/simulate?
Chris
Hi Chris,
We need parameter as below
1.Enable delay
2.Softstart time
3.Discharge time
4.LX (with CLOCK having specific frequency)
5.VOUT PG (including PG delay)
6.TSETP (Slew rate when changing voltage)
Thank you!
Jeff
Hi Jeff,
Thanks for explaining.
Many of these items are specified in the D/S, shown in a figure, or best measured on an EVM.
1. Figure 9-8 shows this as about 70 usec.
2. This is specified as 500usec typical and shown in figure 9-8.
3. The discharge current is specified as 150 mA typical. The time depends on the output voltage, load current, and Cout.
4. The switching frequency is specified as 2.2 MHz and can vary a little with Vin and Vout. It's best measured on an EVM.
5. The rising and falling PG delay is specified in the D/S and shown in figure 9-9.
6. This is best measured on an EVM and depends on Cout, Vout, and the load current step.
Let me know if you have design requirements for a specific application, and I can provide more details.
Thanks,
Chris