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LM5164-Q1: Strange output voltage behavior during simulations

Part Number: LM5164-Q1

We are working on a critical design where converter stability must be a priority and, during simulations, we encountered strange behavior of the output voltage. This behavior is presented both in the Spice model (simulated in LTSpice) and in Webench. The problem does not occur in simulations on Tina TI.
Could you tell us if this behavior in the output voltage will actually occur in practice or is it some kind of problem in the simulation models?
The converter specifications are:
Input voltage: 16.5 to 40V (36V nominal);
Output current 0.2A nominal, 0.8A maximum. We designed it for 0.8A to reduce the capacitor - the simulations were run for 0.8A output current.
Output voltage: 14.5V

Waveforms found:
Webench:

LTSpice:

Simulated circuit:

I understand that the vertical span is small, but such variations worry us regarding the system's stability.

Thank you in advance!

  • Hello Joao,

    Go ahead and reduce Cr to 330pF and check switch node then, I suspect it will stabilize.  thanks.

    David.

  • Hello David! Thanks for answering my question.

    It did change the buck behavior, but it still weird. Also, 330pF Cr is bellow the minimum recommended from equation (7). Webench link:  https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=3DB9026B36891DD1

    Thanks!

  • Hello Joao,

    the Cr generates the ripple voltage for the feedback node, if the ripple is not high enough it can cause double pulsing and instability.  Looks like there is an issue with the standard WEBENCH design that was presented as a solution to your requirements.  there is no reason why you cannot use a small Cr capacitor value of 330pF.  The datasheet is giving starting point recommendations.  You can go with the 300pF Cr, or make it equal to the min recommended value and then reduce Rr such that the time constant remains the same. 

    Hope this helps,

    David. 

  • Hello David, 

    The weird thing is that in TINA TI the power supply works fine, with coherent SW voltages, output behavior and output ripple.
    TINA TI models are simplified or can we trust in the results we get?
    Ca, Ra, Cb were calculated in order to inject a 20mV ripple according to (7), (8) and (9) datasheet equations.

    Below I show the output voltage in LTSpice and the output voltage in TINA TI for the same converter:
    TINA TI:

    LTSpice

    Even though the ripple is approximately the same, it is easy to see that the output voltage at LTSpice has fluctuations and the SW voltage has several "glitches". On the other hand, TINA TI simulation seems cleaner and with regular waveforms.

  • Hello Joao.

    I checked the original design in SIMPLIS and it was unstable.  the glitching is not normal and is the result of the inadequate ripple injection.

    Thanks.

    David.

  • Hi David!

    Thanks for the help so far.
    Still, I believe there is something inconsistent with the models. I simulated the datasheet reference design, shown in the figure below.

    Datasheet design:

    LTSpice design:

    Then, I compared the waveform at full load of the output voltage and switching node, as shown in the datasheet. The switching node, in the LTSpice simulation, continues to present unwanted glitches. I believe that the design presented in the datasheet is validated so that it is possible that there may be a problem in the simulations/models.

    Datasheet waveform:

    LTSpice waveform:

  • Hello Joao,

    Unfortunately, we cannot support LTSPICE other than advise verbally as we are unable to install and use.  suggest you trust WEBENCH and the information I have provided to you.

    Hope this helps.

    David.