LM5069: Power management section - 1uF on source or drain side of external FET?

Hello team, 

The LM5066 and LM5069 datasheets have a very similar recommendation in the "power supply recommendations" section of their datasheets fora 1uF capacitor be placed to reduce common mode voltage seen during transients in some applications. 5066 recommends this be placed between FET source and GND, LM5069 recommends it between FET drain and GND. Are both acceptable? If not, what is the reason these differ?

Thanks very much!