TPS3899-Q1: RESET pin is deasserted when VDD and SENSE are supplied by a positive pulse narrower than the duration of reset time set by CTR

JUN LIU

Part Number: TPS3899-Q1
Other Parts Discussed in Thread: TPS3899

Hi,

In the datasheet of TPS3899-Q1, I don't understand Figure 7-3:

1. What is the meaning of "VDD=SENSE", is the two pins connect together?

2. Since the width of positive pulse on the SENSE pin is narrower than the duration of the reset delay set by CTR (t<td), the /RESET pin should not respond to this pulse . But in the Figure 7-3, /RESET pin is deasserted.

3. Since VDD is 0 after the high pulse, TPS3899 does not work. But it output high puse at that time.

Perhaps I haven't grasp the context of this figure.

7 months ago

0 Jesse Villanueva 7 months ago

TI__Genius 14770 points

Hi Jun,

Sorry for the confusion, the bottom of the VDD=SENSE plot is suppose to be labeled as VDDmin and not all the way to 0V. Yes the VDD=SENSE means that the VDD and SENSE pins are shorted together. The main point of Fig 7-3 is to illustrate that the charging voltage of the CTS and CTR is dependent on the VDD voltage, and for instances where VDD and SENSE are tied together, the user may experience inconsistent timings due to the fluctuation of the VDD.

Jesse

0 JUN LIU 7 months ago in reply to Jesse Villanueva

Prodigy 10 points

Hi， Jesse,

Thank you, I understand your meaning.

I feel this figure is easy to confuse the reader.

The datasheet gives the threshold voltage Vth_cts and Vth_ctr, which are propotional to VDD voltage, equal to 0.73*VDD. So, as the VDD varies, these two threshold voltages vary too. These factors influence the capacitors CTR and CTS 's charging and discharging time sequence. This results in the RESET signal is deasserted even if the VDD/SENSE pins appear positive pulse which is narrower than the duration of reset time set by CTR.

This is my understanding, I don't know if it is right.