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Original question:

UCC21750: PCB Layout guidelines

UCC21750: Gate Driver's output is missing

Raju Baddipadige
Prodigy 200 points
Part Number: UCC21750

Hi,

I'm currently working on a Dual Active Bridge DC-DC converter project, utilizing the UCC21750 gate driver ICs. The switching frequency of the converter is 20kHz, and we are using SiC MOSFETs as the switching devices. However, we've encountered an issue with two of the gate drivers misbehaving. Specifically,  is experiencing a sudden drop in gate voltage to zero, causing the MOSFET to turn off unexpectedly for about 500ns while the input of the gate driver is fine. Strangely, no fault is being triggered from the gate driver IC. 

I've reviewed the PCB layout, ensuring that all decoupling capacitors are positioned close to the gate driver ICs with the shortest possible trace length. I've attached a waveform illustrating the issue, notably occurring at a frequency of 1kHz. Could there be any logic within the gate driver that might explain this behavior at 1kHz?

I wanted to provide further details regarding PCB layout. We have used a ground plane in our high-side gate driver, which differs from the PCB design guidelines recommended for the UCC21750. Despite this deviation, I'd like to highlight that I've utilized ground planes in numerous designs previously without encountering any issues.

Any insights or suggestions you may have regarding this issue would be greatly appreciated.

Gate Driver Problem.pdf

  • 0
    TI__Genius 13760 points

    Hi Raju,

    Thank you for posting to E2E.

    Based on the waveforms the SiC MOSFET was already in the ON-state before the gate driver output voltage dropped. Since the SiC MOSFET being driven was already in steady state before the gate voltage dropped I believe the issue may be coming from other system noise with the 1kHz frequency that is affecting the gate driver inputs.

    • Would you be able to share the schematic and layout of the gate driver circuit?
      • I'm mostly interested in the IN+, IN-, and RST pins. For increased robustness against noise these pins should have a decoupling capacitor (10-100pF) placed as close to the gate driver pin as possible.
    • Would you be able to capture waveforms with the following signals during the failure?
      • Signals:
        • IN+ referenced to GND
        • IN- referenced to GND
        • RST referenced to GND
        • OUTH referenced to COM
      • I would like to analyze noise on these input signals. Use maximum oscilloscope bandwidth and sampling rate, and use a small probing loop to capture the most accurate representation of the signal into the pin.

    Best regards,

    Andy Robles