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Original question:

UCC5880-Q1: Dout Signal Pull-up recommendation

UCC5880-Q1: ADC fault

Yassine Damoh
Prodigy 135 points
Part Number: UCC5880-Q1

Hello,

- What could trigger an ADC fault, besides the high switching frequency (above 50kHz) ? We are (sometimes) seeing an ADC fault when switching at 20kHz with continuous sampling mode. What could be the reason ?

- The fault occurs on a running system, but wasn't able to replicate it on the bench.

- In the datasheet, we can see "Operating the output at frequencies greater than the recommended maximum may cause FIFO (first in, first out) buffer to fill up, triggering FAULT1[ADC_FAULT]." and also "ADC_FAULT may be indicated when INP signal is greater than recommended max". is it dependent  on the output or input? 

- In case it's output dependent, could a glitch on the ASC_EN pin (>tASC_HLD) resulting in an "apparent" high frequency switching, trigger an ADC fault ?

- Is there any dependency to the actual ADC input level and/or noise? forcing the AIx to voltage to voltage higher than the FS (4V) does not trigger a fault.

Thanks

Yassine

  • 0
    TI__Expert 5790 points

    Hello Yassine,

    This sounds like an issue that was present in the very first prototype, but has been resolved in the final product.

    This issue led to the ADC fault reporting when it shouldn't at frequencies below 50kHz.

    Could you read the ID register of the driver, or share the lot trace code (Markings on the package) and we can confirm device is one of the early prototype samples?

    Regards,

    Daniel

  • 0 in reply to Daniel Norwood
    Prodigy 135 points

    Thanks Daniel for the feedback.
    I will get back to you regarding the ID as soon as possible.

    Assuming that the current batch uses one of the first silicon prototype, is there any work around to avoid the ADC fault ? 
    and could you confirm if the ADC fault is only caused by the input INP signal.

    Thanks again,

    Yassine

  • +1 in reply to Yassine Damoh
    TI__Expert 5790 points

    Hi Yassine,

    The ADC fault can be disabled by writing the ACT1 register bits 5:4 to 00b. (See datasheet table 6-18)

    This will allow testing with current silicon without interruption. 

    The ADC fault is caused by a failed ADC conversion, since the conversion rate is related to the input PWM, there is a relationship that caused unexpected faults. The ADC value in the register is still valid, but if there is a fault may be delayed 1 PWM cycle. I see no risk disabling the fault detection in the ACT1 register.

    For the ID register, if it reads 0x0000 it is the early prototype with the issue.

    Regards,

    Daniel Norwood