Hi Jeff,
Thanks for the files and waveforms.
What is the failure rate of the MOSFET damage? Can the customer probe the waveforms of DR1H, DR1L and SW1 at the time of failure?
And can they zoom in the waveform in 5ns/div?
About the schematic:
1. For the EC16, I don't find the datasheet online, can you share this with me so I can check the COMP parameters. Or the customer can also check the phase margin by observing the output voltage ripple during load transient as below note mentioned.
https://www.ti.com/lit/pdf/slva381
2. Recommend to change R538=R537=0ohm;
3. What is the input voltage range, output voltage range and max output current? Recommend to set lower average inductor current limit with higher value of R555.
4. I also don't find the information of L45, what is saturation current for this? Recommend to select the inductor with saturation current > average inductor current limit value.
About the layout, it look poor especially with the relief connection of GND connections which would introduce large parasitic parameters into the power loop and cause higher voltage spike.
1. Use solid connections for all GND connections.
2. Add the 0.1uF/0402 ceramic capacitor close to Vin and GND net.
3. Add one 0.1uF/0402 output ceramic capacitor more close to Vout and GND pins. And use solid connection for GND connection.
4. Use Kelvin connection for ISP and ISN connections.
5. Recommend to add one more 0.1uF/0402 ceramic capacitor close to Vout vias and GND plane at the bottom layer.
BRs,
Bryce
