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BQ25628E: Pullups and VREF

Simon Merrett
Prodigy 100 points
Part Number: BQ25628E

I'm designing a USB 5V powered single cell lipo charging circuit. We want to have I2C communications + interrupt to a 3.0 - 3.3V logic level microntroller to monitor the BQ25628E registers. I understand that in the typical application circuit, VREF is the logic voltage of the host MCU, although that doesn't seem to be explicitly stated in the datasheet.

1. Please could you confirm what VREF is intended to be?

Furthermore, we seek to implement the lowest power circuit, so the host MCU will be entering sleep modes. We plan to power the I2C SDA/SCL and BQ25628E INT pullups with 10k resistors to a GPIO on the MCU, so that the pullup rail can be powered down for lowest power operation.

2. Please can you expand on how much leakage current the I2C and INT pullups are expected to draw with e.g. 10k Ohm resistors to 3.3 V (datasheet gives values for 1.8V) and also advise on the best scheme for lowest leakage / quiescent current in the surrounding / supporting circuitry around the BQ25628E?

3. Would we be better off leaving the I2C and / or INT lines pulled up during low power modes of the MCU for lowest leakage or can they be pulled to ground when the MCU is sleeping?

  • 0
    TI__Guru 50151 points

    Hi,

    1. The I2C INTERFACE (SCL, SDA) logic specs are on page 15 of the d/s. 3.3V logic should be ok.
    2. Not available.
    3. Please check on the customer design boards.

    Thanks,

    Ning.

  • 0 in reply to Ning T
    Prodigy 100 points

    Hi Ning, thanks for your response.

    1. I can't see logic voltage information on page 15 of the datasheet, only max clock speed: 

    There is also no mention of INT pullup ranges either as far as I can see. I will work off your advice that 3.3V should be ok.

    2. OK

    3. I can ask on the customer boards but this is more about chip behaviour - what would the leakage current be if the SCL/SDA lines were grounded by a sleeping MCU? EDIT: also, I have just had a look for "customer design boards" which I presumed was an area of the TI E2E forum but I cannot find it - all queries seem to point back to the Power management > Power management forum, where this thread is posted. Please could you give me more detail on what you're suggesting and some instructions how to do it?

  • +1 in reply to Simon Merrett
    TI__Guru 50151 points

    Hi,

    1. Page 14

    3. It's mainly the host to drive SDA and SCL. The SCL and SDA pins will be in high impedance mode if not driven.

    Thanks,

    Ning.