TPS25940-Q1: why the FLT pin is low level when without input?

Hi Arush,

I know that is an active low pin. I'm just confused that where is the FLTb pin pulled up? (which power rail?) in this Figure 10-24. Because without Vin and Vout, the FLT pin is still active low.

Steve

Hi Steve,

Most likely it is pulled up to external power supply in this image. (I cannot confirm the exact thing here). The internal implementation is done using open-drain FET with gate being controlled by SWENb signal (not of switch enable). Here when UVP is triggering, SWEN becomes low so SWENb is high and the FLTb FET is on so FLTb low output. 

Best Regards,
Arush

Hi Arush,

But if the device is pwered by Vin our Vout, when Vin and Vout is removed, the internal open-drain FET can still be controlled to be on?

Hi Steve,

If the device is powered on (Not talking about the passFET but the eFuse itself), then the open drain FET for FLTb pin will be driven to appropriate levels but if the device is powered off, then the FET can't be controlled. In that state, FLTb will be low. 

Best Regards,
Arush

Hi Arush,

I understand, but if the FET can't be controlled when device is powered off, shouldn't FLTb be high dute to the pull up connection with external power supply?

Hi Steve,

Oh! understood your concern now. I think you are correct, and it looks like in the above waveform, FLTb is pulled up to Vout then. 

I apologies for causing confusion. This is an old device and people who did these datasheets already left the team so there was some gap in communication.

Best Regards,
Arush

Hi Arush,

So, if I can understand it that way, when the FLTb pin is pulled up to external power supply, and if the Vin and Vout is removed (device is powered off), the FLTb will be high since FET can't be controlled.

Since FET cannot be controlled, yes it should be high. In case the FET have some trapped charges in parasitic, then it can result in some leakage path which can reduce the voltage level.

Best Regards,
Arush