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UCC5390ECDWVEVM: How to configure OUTPUT of UCC5390E when to use drive 2 SIC fet ?

Zoe Yang
Intellectual 2210 points
Part Number: UCC5390ECDWVEVM
Other Parts Discussed in Thread: UCC5390

Tool/software:

Hi team,

Our EVM only showed wrong pin out of UCC5390 on the output. Can you help provide reference schematic and layout when driving two parallel SIC FET by using UCC5390E?

  • 0
    TI__Mastermind 19256 points

    Hi Zoe,

    The EVM is configurable to work for either package variant. 

    To drive two parallel FETs with the E version, they could try something like this:

    Best regards,

    Sean

  • 0 in reply to Sean Cashin
    TI__Intellectual 2210 points

    Hi sean,

    Do we have recommendation layout on Clamp pin for driving two SIC in parallel? 

  • 0 in reply to Zoe Yang
    TI__Mastermind 19256 points

    Hi Zoe,

    If you use the UCC5350M, you should put 1-2.2Ω between CLAMP and each gate. That will still be below the inductance floor of the gate loop impedance at high frequency, but it will help soften any FET mismatch during turn-on due to Vth process differences.

    Best regards,

    Sean

    Clamp Circuit suggestion:

    Miller pull down impedance: Injection is usually >50MHz