TPSM8D6C24: How to check the SW node voltage

Part Number: TPSM8D6C24
Other Parts Discussed in Thread: , TPS546D24A

Tool/software:

Dear Sirs and Madams,

We are currently mounting the TPSM8D6C24 on a board and checking its operation.

When the output voltage was set to 800mVdc, the output ripple voltage was observed with an oscilloscope and found to be a sine wave of approximately 70mVpp with a period of approximately 50kHz.

Because the switching frequency is set to 650 kHz, it is believed that with 2-phase operation the ripple voltage period will be 1.3 MHz, and that the low-frequency operation of approximately 50kHz is unrelated to switching.

So, I would like to confirm for the operation of the switch node of the TPSM8D6C24, but the SW_A/B terminals assigned to the bottom of the TPSM8D6C24 do not have a through-hole on the board, so they cannot be measured with a probe.

Is there a way to confim the switch node from the surface mounted on the TPSM8D6C24 module?

Regards,

2 months ago

0 Calan Elaya 2 months ago

TI__Expert 5045 points

Hello,

Savith will respond to this in few days.

Thanks,

Calan

0 Savith Kumar Rayakanti 2 months ago

TI__Intellectual 2450 points

Hi MM

Can you share schematic and any design tools you have used for this design, specifically the MSEL1 (frequency and compensation) selection and details on the output capacitors

Thank you

Savith

0 MM 2 months ago in reply to Savith Kumar Rayakanti

Intellectual 460 points

Hello Savith,

The switching frequency of the TPSM8D6C24 is set to 650kHz.

The circuit diagram configuration is based on TPSM8D6C24EVM-2PH.

MSEL1_A : Pulled up with 21.5k and pulled down with 31.6k (R2G is 10, Register divide code is 8)

MSEL1_B : GND

2ph_1output_TPSM8D6C24_TPS546x24y_ExcelCalculator_SchematicLayoutChecklist_bodeplot_V2p2_20240624.xlsx

TPSM8D6C24 2-Phase Power Module Evaluation Module User's Guide (Rev. A)

Regards,

0 Savith Kumar Rayakanti 2 months ago in reply to MM

TI__Intellectual 2450 points

Hi MM

Looking at the excel calculator attached and assuming the derating of cap selected is correct

the Fcoi calculated is 216.67kHz which is max current loop bandwidth

But with selected compensation code 25 the BW-ILOOP is 270kHz which make the current loop instable

for a better compensation

1. Decrease the Compensation config to 15 to keep the BW-ILOOP with in the spec

and the transient spec is at the boundary of 12mV as you can see the under shoot and over shoot is 1.51%

2. If 1.51% under and overs shoot is not acceptable

Keeping the compensation config at 15 and reducing the cout will aid with transient spec

you can keep the config comp at 15 and increase the gain of Gain of voltage loop with PMBus will help in meeting the Transient spec with good phase margin

I am attaching 2 excel sheets with and without change of Gain of voltage loop

TPS546x24y_ExcelCalculator_SchematicLayoutChecklist_bodeplot_V2p2_07052024.xlsx

TPS546x24y_ExcelCalculator_SchematicLayoutChecklist_bodeplot_V2p2_07052024_GMV change.xlsx

Note:

while Changing the GMV in using PMBus and storing it to NVM

you must Pin detect override so after device power cycle it doesn't detect pin strap resistor values and take the values from NVM

Thank you

Savith

0 MM 2 months ago in reply to Savith Kumar Rayakanti

Intellectual 460 points

Hello Savith,

By changing the switching frequency from 650kHz to 900kHz and increasing the capacity of the output capacitor (5,584uF to 9,306uF), the amplitude due to low frequencies has been improved.

2ph_1output_TPSM8D6C24_TPS546x24y_ExcelCalculator_SchematicLayoutChecklist_bodeplot_V2p2_20240624_test.xlsx

However, the period of the output ripple voltage appears to be approximately 926kHz(=1.08us), and from the waveform it does not appear to be a 2-phase operation.

Is it difficult to observe the switch node from the component side of the module in order to confirm whether the output ripple voltage is operating correctly in 2Phase?

I understand that it is best to be able to observe the SW_A/B terminals of the module, but on our customer's board, the SW_A/B terminals are laid out directly under the module and cannot be observed.

Regards,