Tool/software:
Hi,
The following image shows how we are connecting an FPGA to the HD3SS3220 mux and then to a USB C connector. Could you let me know if the AC decoupling caps are correct. They are all 0.1uf.
Thank you
Liam
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Tool/software:
Hi,
The following image shows how we are connecting an FPGA to the HD3SS3220 mux and then to a USB C connector. Could you let me know if the AC decoupling caps are correct. They are all 0.1uf.
Thank you
Liam
Liam
HD3SS3220 high speed signal pins common mode voltage (Vcm) is from 0 to 2V. If the FPGA common mode voltage can meet HDS3SS3220 Vcm, then there is no need to have AC coupling capacitors between the FPGA and HD3SS3220 since you want to use the FPGA Vcm to set the HD3SS3220 Vcm.
If FPGA Vcm can't meet the HD3SS3220 Vcm, then you need to have AC coupling capacitors between the FPGA and HD3SS3220, but then you also need to provide external biasing to set the HD3SS3220 Vcm.
For more details, please see this E2E FAQ, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1342811/faq-tmuxhs4212-when-and-how-to-ac-coupling-the-passive-mux?tisearch=e2e-sitesearch&keymatch=FAQ#.
Thanks
David
Hi David,
I think the FPGA can meet the common mode voltage requirements so I’ll remove the caps from the FPGA to the HD3SS3220 mux. What is confusing me is that the design I have shown works on a number of circuit boards and there are problems with some others that could be due to different issues. Could you explain why some of our circuit boards work with the caps in place?
Thanks,
Liam
Hello,
Due to a US Holiday, the response to your question may be delayed. We will look into your question when we return tomorrow, July 5th. Sorry for the wait and any inconvenience it may cause.
Thanks,
Ryan
Liam
With AC coupling capacitors on both sides of HD3SS3220, the HD3SS3220 common mode voltage is floating, so HD3SS3220 may or may not work properly.
Thanks
David