TPS2660: Check the circuit diagram and AW

Hi Amrit,

Thank you for your support.

I sent you a private message.

Best Regards,
Ishiwata

Hi Amrit,

Thank you for checking the schematic and the AW.
I appreciate your support.

I have some additional questions about the layout.

(1) In the EVM layout, the RTN terminal is connected to the TOP, BOTTOM, and GND layers.
The customer is concerned that RTN may be affected via the digital GND when performing a burst test.
It seems better to separate the RTN terminal from the GND plane a little, but what do you think?

(2) Questions about Power PAD (RTN)
Does it need to be extended a little like in the layout below?
Do you know the reason for the slight extension?

Best Regards,
Ishiwata

Hello Ishiwata,

Shuji Ishiwata said:

(1) In the EVM layout, the RTN terminal is connected to the TOP, BOTTOM, and GND layers.
The customer is concerned that RTN may be affected via the digital GND when performing a burst test.
It seems better to separate the RTN terminal from the GND plane a little, but what do you think?

From schematic that you have shared, RTN is separated from Power GND.Shorting RTN and GND will disable the reverse polarity protection.

Yes, it's better to sepertate RTN terminal from GND plane.

Shuji Ishiwata said:

2) Questions about Power PAD (RTN)
Does it need to be extended a little like in the layout below?
Do you know the reason for the slight extension?

That extension is provided to accommodate more heat sink vias. Depending on your temperature range you can skip this.

Thanks 

Amrit 

Hi Amrit,

Thank you for your answer.

I have a follow-up question about (1).

The customer has prepared RTN planes on the TOP, BOTTOM, and GND layers.
Will the RTN planes be affected in the burst test?
Also, is there a case where RTN will be affected via Vin and Vout?
The customer is concerned that the RTN plane will be susceptible to noise if it is too wide. What do you think about this?

Best Regards,
Ishiwata