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TPS51285B: dead time

Fred Cheng
Expert 5750 points
Part Number: TPS51285B
Other Parts Discussed in Thread: TPS51285A, , CSD17302Q5A

Tool/software:

Hi team,

customer want their switching deadtime could be larger than 10nS spec,

I know it's related to MOS Qg as well, but since it's fixed.

is there any workaround we can do on the schematic on snubber value?

6683.SCH.pdf

schematic above:

  • 0
    TI__Guru 56965 points

     

    Fred Cheng said:
    is there any workaround we can do on the schematic on snubber value?

    A switch-node snubber does not affect the UGATE to LGATE dead-time.

    Do you have part number and specification for the SINOPOWER high-side MOSFET?  The PK600AB part number came up with a part from a different manufacturer that looks like it should be turning off in under 20ns.

    It's taking about 35ns for this MOSFET to turn off and the switch node to drop, which is a very long time for the 1.9Ω driver pull-down to discharge the high-side MOSFET with PR4508 = 0Ω, and that long discharge time is what is driving the need for more dead-time on the UGATE falling to LGATE rising dead-time.

    It should also be noted, when driving 2 MOSFET from the same gate-drive, it is generally recommended that each MOSFET have a separate gate drive resistor so that MOSFETs with different gate threshold voltages can switch at the same time and the MOSFET with the higher threshold voltage will not wait until after the other MOSFET has switched before switching.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    so they have main source Sinopower and Nikosemi,

    but both sources need larger dead time by changing other MOS.

    customer prefer workaround without changing MOSFET first , do you have ideas?

    .

    .

    below is HS and LS MOS both come from Niko semi.

    084.00600.0B37_PK600BA_HS.pdf084.PKCH6.0037_PKCH6BBWIC_LS.pdf

    and below is the sinopower HS and LS

    084.04378.0037_SM4378_HS.pdf

    084.04508.0037_SM4508NHKP_LS.pdf

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    The TPS51285A does not provide user programmable dead-time control.  The dead-time can only be controlled by the gate-drive strength.  While we could delay the turn-on of the low-side MOSFET with a series gate drive resistor (not currently available in the schematic) that is likely to result in cross-conduction during LGATE turn-off and UGATE turn-on.

    That said, the turn-off times shown in the waveforms do not correlate with the gate charge and gate resistance values provided in the MOSFET datasheets, so I would recommend changing the values of the bootstrap and gate drive resistors and making sure they match the values listed in the schematic.

    Even with 2Ω of gate resistance and 1.9Ω of driver pull-down resistance, it should not take 35ns to discharge 7.5-8nC of gate charge from the high-side MOSFET.  If the series gate-drive resistor is 0Ω a review of the gate drive and switching node return length might be required to determine why the high-side MOSFET is turning off so slowly.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    thank you, how do you recommend bootstrap to change?

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    My apologies.  That should have been "checking" not change

    The schematic shows 0Ω resistors for the UGATE to MOSFET gate resistors PR4505 and PR4508 and 1.5Ω resistors for the bootstrap resistors PR4507 and PR4506.  Check these resistor values on the board to make sure those values are correct.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    they have checked it and there's nothing weird founded.

    this is p2p RT6575's deadtime, which looks wider than us with same MOS

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    Yes, the Richtech RT6575 has longer dead-times than the TPS51285B.  This longer dead-time results in increased body diode conduction with each switching cycle, higher MOSFET power dissipation and reduced efficiency.

    What is very strange in the comparison is the significant difference in the fall-time of the gate drive between the TPS51285B and the RT6575, given that they have the same driver strength, they should be producing the same fall-time unless the gate drive resistance is different.

    The waveforms from the Richtech device are showing a 12ns fall time.  What we expect from a 7.5nC MOSFET discharged from 5V through with a 1.9Ω resistance and MOSFET gate resistance of 1-2Ω.  We would not expect the MOSFET fall time to be 37ns with a 14ns plateau unless there is an issue with the series resistor, solder joints or damage to the device.

    I would recommend reflowing the UGATE pins, MOSFET gate pins and replacing PR4505 and PR4508 with 0Ω resistors to make sure the issue is not in those paths.  If the TPS51285B is still showing a UGATE falling time of 37ns, replace the TPS51285B as it may be damaged.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    they said the soldering is from factory machine and handed, 

    so shouldn't be any flaw about soldering.

  • 0 in reply to Fred Cheng
    TI__Genius 11435 points

    Hello,

    Peter will respond to this next week.

    Thank you,

    Calan

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    Then I would recommend changing the TPS51285B as the UGATE falling time does not appear to be correct and the device may have been damaged.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    they tried lots of TPS51285  ICs on other boards but see the similar waveform, so this is not single case. please check the layout below.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/242002_2D00_SC.0627WPH2213.7z

    they manage to insert  1 ohm resistor at LGATE but still fail Lenovo spec (8.2ns < 10ns)

     also they've change HSMOS Qg to 11.5nC from 13.5nC is also fail (7.4ns < 10ns)

           

    there're two question from customer that quite urgent this time, if the layout is consider ok.

    1. what Qg value do you suggest for our controller HS MOS?

    2.do you have a suggested TI MOSFET that can make the deadtime meet the spec?

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points
    Fred Cheng said:
    they manage to insert  1 ohm resistor at LGATE but still fail Lenovo spec (8.2ns < 10ns)

    Why does Lenovo have a minimum 10ns dead-time spec?  That is an arbitrary and fairly large minimum dead-time spec which is negatively affecting their efficiency.

    Fred Cheng said:
    1. what Qg value do you suggest for our controller HS MOS?

    As you noted, a higher gate-charge is resulting in slower HS turn-off, which translates into less dead-time.

    For an alternate TI MOSFET in the same 5mm x 6mm 8-pin thermally enhanced package, I would recommend trying the https://www.ti.com/product/CSD17302Q5A 

    It has a lower Rdson for 5V gate drive (9mOhms versus 12mOhms) and much lower total gate charge (5.4nC versus 8nC) 

    Fred Cheng said:
    if the layout is consider ok.

    The layout looks ok, though there are some places it could be improved:

    As I noted before, when operating two MOSFETs in parallel, it is generally best to have a separate series resistor in each gate drive to allow the MOSFETs to have different threshold voltages during switch transition.  This helps balance switching losses and thermals between the MOSFETs.

    Routing the SW connection, which is the return for the high-side gate-drive directly under the gate drive trace for as much of the gate drive path as possible will minimize loop area and inductance, providing the best turn-on and turn-off possible.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    the whole goal is to pass all the spec of Lenovo, we passed efficiency with high margin,

    there's one last fail left.

    anyway, thank you for the suggestion I'll forward to them.

    .

    .

    would you show us a theoretical maximum Qg that they need to pass this 10nS deadtime?

    so it can be more convincing to use our low Qg MOSFET.

     (total deadtime include dead time of the controller itself plus the charging and falling time of HS MOS gate)

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    The TPS51285B uses Adaptive Dead-time Control where where the output voltage on the driver is sensed during the falling edge, starting a 12ns or 20ns dead-time period (specified in the datasheet) before turning on the complementary driver.  The exact dead-time produces depends on the MOSFET falling time after the detection and the complimentary MOSFETs rise-time.

    Since the Driver is detecting the turn-off of the UGATE at about 2V, it's the gate charge from 2V to 0V, and the LGATE rise-time, not the total gate charge which defines the dead-time.

    The UGATE pull-down strength is given as 1.9Ω.  From 2V to 0V, the average discharge current is 0.5A, but with a target spec of 10ns there is only 2ns to discharge Vgs with 0.5A.

    The LGATE turn-on time will add a small additional delay, about 3ns, leaving about 5ns or 2.5nC @ 2V to turn off the high-side MOSFET before the dead-time would be less than 10ns.  - The CSD17302Q5A has 1.5nC of gate charge at 2ns.

    The real problem is that Lenovo's arbitrary 10ns minimum dead-time spec is extremely close to the nominal 12ns dead-time spec of the TPS51285B.  If there is any way to discuss the 10ns spec with Lenovo and convince them to decrease it for controllers using Adaptive Gate Delay dead-time control like the TPS51285B, it would be much better.

  • 0 in reply to Peter James Miller
    TI__Expert 5750 points

    Hi Peter,

    this is so detail, and I like it, thank you.

    i've forward them the beauty of adaptive dead time control, 

    but now they try to find it and match to the datasheet spec.. 

    they found the deadtime  between  SW is close to 0V  and the rising of LSGATE is smaller than the deadtime in our datasheet,

    but is it the right way to prove this?

  • 0 in reply to Fred Cheng
    TI__Guru 56965 points

     

    The 12ns from the datasheet is measured without capacitive loading on the gate drivers so there is no slope to contend with.

    It's also not measured from SW to GND, the high-side gate is measured from UGATE to LL (The gate-source voltage of the high-side FET) 

    If you measure the period of time the switching node is negative under positive load, that is a pretty good measure of the actual anti-cross conduction time.  For internal MOSFET products, we often tune the gate drive for this node to be less than 0.3V for 5-8ns to ensure there is no cross-conduction while maximizing efficiency.