• State
  • Replies 4 replies
  • Subscribers 64 subscribers
  • Views 90 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

TPS6594-Q1: The INT pin is low while all the power supply is normal and the INT signal may lead to SOC burning abnormal

Tianyuan Zhou
Prodigy 10 points
Part Number: TPS6594-Q1

Tool/software:

Dear Ti expert,

Soc cannot be burned in two of our boards. The EN_DRV pin and INT_N pin is low and all the power supply is normal. I read the INT registers and found it's related to GPIO4 and MISC interrupt. I mesured GPIO4 pin and it's 1.8V. So why INT pin is low and where the problem is. Please help to check. thanks.

Enclosed all the register values for detail.TPS6594 Register values.xlsx

  • 0
    Prodigy 10 points

    Dear TI expert,

    Is there any update from your side?

  • 0 in reply to Tianyuan Zhou
    TI__Guru 69876 points

    Hi Tianyuan,

    Can you please share the full part number of the device so that we know which NVM you are working from, or whether you are using a custom NVM? 

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Prodigy 10 points

    Hi Katie,

    The full part number is TPS6594741FRWERQ1. The NVM is defined by Qualcomm and TI.

  • 0 in reply to Tianyuan Zhou
    TI__Intellectual 945 points

    Hello Tianyuan,

    To assist you in finding the root of this problem, could you provide answers to the following questions?

    1. What is meant by "Soc cannot be burned"? Could you describe the process that is being performed when the described behavior is observed?
    2. What is the GPIO4 pin connected to? It seems that the GPIO_4 signal going high has caused the GPIO4_INT bit to be set. Would this behavior be expected in the customer's application?
    3. Do the PMIC rails restart at any point? Please monitor the power rails and let me know if any observed behavior of the PMIC is indicative of the PMIC having been reset during this procedure.

    4. I am not sure at what point this behavior is being observed. Is it possible to clear these interrupts as they appear? Please let me know if you are able to test this and whether the interrupts are set after being cleared.

    Best regards,
    Jude Stehling