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LMR38020: LMR38020FDDAR - Dip on the PG line 14us after the rise of the line

Part Number: LMR38020
Other Parts Discussed in Thread: TPS62826, , TPS62826AEVM-126,

Tool/software:

Hi, Team!

I have 2 different boards, both populated with LMR38020FDDAR chip and I observe this strange dip on PG line 14us after the line has risen:

On one board we have 3.3k pull-up resistor on the PG line and see this:

On the other board I have 10k pull - up resistor on the PG line and see this :

The schematic is the folllowing:

I have scoped the EN line, the VIN line and the VOUT line of this chip against the PG and there is nothing strange going on there, no sudden transients or power outs.

I am wondering where this dip is coming from? Is this something internal to the chip?

Thank you very much!

  • Hi Kristina,

    I suspect it is due to the LED D46. When output has risen to the forward voltage of D46, D46 conducts, which will add an increased load to the 5V rail. If the output dips low enough, it can result in PGOOD pulling low, so it will draw some current and so the larger your pull-up resistor, the larger the drop you see. Can you check by removing the diode? 

    Also, does the issue track across the IC?

    Thanks,

    Richard 

  • Hi, Richard!

    Thank you very much for your reply.

    We have scoped the 5V rail at the same time as we scoped the PG and it's stable, we've also run substantially more challenging tests with excellent rail deviation that remains within the PG thresholds. We have also taken the LED off the board after that to be 100% sure, but the dip does not go away. We believe there must be something else that is causing it.

    To reiterate, we have that behaviour happening on 2 different projects with the same part populated.

    Could you please suggest any other reasons that might be causing the dip? 

    Thank you very much for your help.

    Best wishes,

    Kristina.

  • Hi Kristina, 

    I see. The possible case for PGOOD going low is OV/UV, current thermal, thermal shutdown. What are your operating conditions?

    What is connected to the PGOOD pin other than the pull-up? Can you monitor VIN, VOUT, PGOOD, and inductor current during startup and for the steady-state cycle so that we can see the start-up as well as the PGOOD dip under two scenarios:

    1) With any external connections connected to PGOOD

    2) With external connections connected to PGOOD disconnected, so that the only thing pulling up is the 5V rail.

    Thanks,

    Richard  

  • Hi, Richard!

    Thank you very much for your reply.

    We have tested for OV/UV, and took thermal captures with thermal camera. There is nothing that would flag an issue.

    PGOOD is feeding into the EN pin of another TI chip TPS62826ADMQ.

    There is nothing else except that pull up connected to the PGOOD of the LMR38020FDDAR.

    1) Here is the capture with the external connections connected:

    Red - Vin (24V)

    Blue - PGOOD

    Green - current through the inductor

    Yellow - FB

    Here is also zoomed out capture of the current and PGOOD:

    We have noticed that current before the PG rise is at a stable frequency, however once the PG rises it looks like the chip is performing pulse skipping, then is at some other frequency and only after the dip it recovers to the initial frequency that was seen before the PG line rise.

    Also tested with additional 1A load on the 5V output:

    2) We have then disconnected the R12, to disconnect the downstream connections. and connected the R9 to TP7, so that it is still pulled to the 5V.

    So, the dip disappeared once the downstream connections got disconnected:

    Blue - PGOOD

    Green - current throught he inductor

    Yellow - FB

    Do you have any suggestions to why the downstream connection of the chip TPS62826ADMQ would cause a dip?

    Thank you very much for your time.

    Best wishes,

    Kristina.

  • Hi, Richard!

    A few more updates on this.

    We have decided to try something else as well.

    We put the 0 ohm link R12 back. Lifted the pin 6 of the U2 up, connected a 3k3 res vertically and added thin wire on top to connect to 5V. The EN line on 3V3 regulator is just pulled to 5V with the R9. This way the PGOOD is disconnected from the EN pin of the U4.

    Blue – TPS62826ADMQ EN pin

    Yellow – LMR38020FDDAR PG pin

    Please ignore the spike on the yellow trace, this is noise, and was not present when rescoped.

    As you can see the EN pin rumps up in accordance with 5V rump up, which is expected

    When zoomed in on the PG line the dip is not there.

    The next test we did was adding 100 ohm resistor between the PGOOD pin and its pad and scoping on both sides of the resistor to see which side has the problem, the PG or the EN:

    Yellow - TPS62826ADMQ EN pin

    Blue - LMR38020FDDAR PG pin

    The scoping was done multiple times and, we see the dip on the PG pin being larger than the EN side consistently, indicating that the problem is on the PG side.

    Please, share your thoughts on this.

    Thanks for your help!

    Best wishes,

    Kristina.

  • Hi Kristina,

    I'll take a further look next week, but one thing I noticed is that if the LMR38020 PGOOD pin is driving the EN pin, why does the TPS62826 EN rise first? I would expect the timing to be the opposite, right? In this case, 

    Is it possible for you to drive the TPS62826 EN pin by pulling it up to the input pin instead and see if the dip occurs? I suspect maybe there is some noise injected back into the PGOOD pin from the TPS6286 starting up that may cause the dip. 

    Thanks,

    Richard 

  • Hi, Richard

    Thank you very much for your reply!

    After rigorous investigation of the potential cause of this, we could not find an issue with our design, so we have ordered two evaluation boards: TPS62826AEVM-126 and LMR38020EVM.

    We have connected them together without changing any components populated on the boards. We have connected the Vout of the LMR38020EVM into the Vin of the TPS62826AEVM-126. We have also connected the PG line of the LMR38020EVM into the EN of the TPS62826AEVM-126. They powered up alright, however when we scoped the EN line, we observed the same behaviour : the dip of 2.2V,  14us after the rise of the line:

    We have then tested just TPS62826AEVM-126 in isolation. We have powered it with 5V and pulled the EN line up to VIN with the 27.8k ( same as the LMR38020EVM PG pull-up) . And saw the dip on the ramp up of the EN line:

    So, we think the dip is caused by the TPS62826ADMQ chip itself and not anything external to it.

    Any suggestions why this is happening?

    Since we see this happening on the evaluation boards we know this is not to do with our particular design, but would like to know the reason why this is happening and how we could use the chips such that we minimise this problem.

    Thank you very much for your help!

    Best wishes,

    Kristina.

  • Hi Kristina,

    This question about the TPS62826ADMQ chip is best answered by the LVB folks. I've looped them in this thread.

    Cheers,

    Richard

  • Hello Kristina,

    this thread seems to be duplicate to another thread: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1431247/tps62826a-dip-occurring-on-the-en-line.

    I will close this thread and continue the support in the other thread.

    Best regards,

    Andreas.

  • Hi, Andreas

    You have mentioned increasing pull-up strength to minimise the blip.

    Could you please advise what is the current capabilities of the PG pin? How strong of a pull-up can we use? Given that we are pulling the PG to 5V.

    Thank you.

    Best wishes,

    Kristina.

  • Hi Kristina,

    it is recommended to limit the current into the PG pin of the LMR38020 to 5mA (see section 8.3.5 in the datasheet). So when connecting the PU to 5V its minimum recommended value would be 1kΩ.

    Best regards,

    Andreas.