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UCC27223: locking up at power up

Part Number: UCC27223
Other Parts Discussed in Thread: LM2104, UCC27311A

Tool/software:

Referencing the schematic from the data sheet, copied below:

I am getting very predictable, very repeatable, unexpected behavior as follows:

- When voltage is applied to VIN for the first time, the IC does not startup, and VOUT remains low (aka cold start).  PWM Input and ENBL input sequencing are shown in the scope images below.

- Next, if VIN is dropped to 0V and then VIN is turned back on within 40 seconds, VOUT will come up and the system behaves nominally (aka warm boot).

Instead, if VIN is dropped to 0V and then VIN is turned back on after 50 seconds, the IC does not startup, and VOUT remains low, same as cold start. 

- When the circuit is "locked up" but VIN is still ON, if I drop ENBL low then go high again, the UCC27223 does not start up, i.e. it is still latched off.

- When the circuit is "locked up" but VIN is still ON, if I drop PWM input low then go high again, the UCC27223 does not start up, i.e. it is still latched off.

I have captured the "cold start" and "warm boot" events on a scope, as shown below. Ch1 (blue) = VIN, 5V/div. Ch2 (green) = VLO, 2V/div. Ch3 (red) = ENBL, 2V/div. Ch4 (magenta) = IN (PWM Input) 2V/div.

No startup image (cold start), 2mS/div:

Normal startup (warm boot), 2mS/div:

I can not see any difference in the ENBL or IN signals in the images above prior to startup that would give me reason to think those signals were causing the lock up.  I do notice that VLO (Ch2) starts at a slightly higher voltage (around 0.4V) during warm boot before VIN is turned on, indicting that VLO has not completely decayed to zero.

Additional information about the circuit: R1 = 4.7Ohms. C1 = 100nF.  Total gate charge for the FET is 31nC.  I increased C1 to 200nF with no effect.

I have a 360K resistor from ENBL to GND.  Because of the 110k impedance inside the UCC27223, this limits the ENBL voltage to around 5V.  I have also tried adding a 100nF capacitor in parallel with my 360k resistor to slow the rise of the ENBL signal.  This had no effect (other than slowing the rise of the ENBL signal) - the described startup anomaly does not change.

C2 = 2.2uF + 100nF in parallel.  CIN = 3 x 10uF (0805) + 100nF in parallel.

There is no Cout capacitor in the circuit.  I have tried adding Cout (.1uF ceramic, 100uF electrolytic) but I get the same results at startup.

It seems to me that there is some internal circuit in the UCC27223 that doesn't like the startup sequencing, or is learning about the circuit.  It fails to start up the first time, but if power is cycled while this info is retained inside the UCC27223 (within a 40 second window) then the UCC27223 will allow the output to turn on when power is cycled.

The VIN power is applied by turning on a PFET in series with a 16V battery.  If I instead use a bench power supply that ramps up relatively slowly (20mS) as a power source instead, the lock up NEVER occurs regardless how long the UCC27223 has been turned off.

It is probably not feasible to turn on the PFET slowly.  However I could turn the PFET on for 10mS, off for 100mS, then back on (or something like that) as a workaround.  However I don't want to employ that "trick" until I understand the root cause of the issue.

  • Hello,

    I do not see the PWM input switching in the first scope shot. The output will not turn on until the PMW input starts switching.

    Is the second screenshot after VIN was removed then reapplied? 

    This is also a very old part and I recommend moving to a newer alternative such as LM2104 or UCC27311A.

    Thanks,

    Walter

  • Thanks for your response.

    Ch4 (magenta) is the PWM input signal.  The signal is high before EN (Ch3, red) goes high.  The PWM signal is not oscillating/switching on and off.  The signal is generated from hysteresis feedback so until the high side FET turns on the first time the PWM stays high.  In the first screen shot the UCC27223 does not turn on: it is latched off. The second screenshot is after removing VIN and reapplying.  If this power cycling is done within 40 seconds, the UCC27223 will start running normally.  If power is turned off for more than 50 seconds, then applying power causes the UCC27223 to latch off and not start up, same as a cold start.

    As explained in my previous post, dropping the PWM IN low then high again without cycling power does NOT allow the circuit to start up.  Also cycling the EN signal does not allow the circuit to start up.

    I will look at the parts you suggested.  I wish I had known sooner.

    Update: I looked at the LM2104 and UCC27311A.  Neither have the predictive gate drive feature of the 27223.  I am switching at 300-400kHz (hysteresis mode, so frequency varies).  Efficiency is very important (battery powered device).  I was "sold" on the predictive gate drive but now you have me wondering if maybe a fixed dead-time would be OK.  For the UCC27311A I would have to add inverter for the low-side PWM input: certainly not the end of the world.  I am curious to know if TI has found that the predictive gate drive is not much of a benefit/selling feature, which is why it is being depreciated.

  • Hello,

    Can you send a schematic of the PWM input hysteresis circuit? 

    The predictive gate drive feature appears to only have been used for the UCC27221/2/3 devices 20 years ago. I will ask my team if we have a better alternate solution.

    Thanks,

    Walter

  • Hi Walter,

    I am unable to publicly share the circuit.  I will send a friend request to you and maybe we can work something out.  After further consideration and lack of explanation of the internal workings of the UCC27223, I am wondering if the problem lies in the charge pump: At the first bootup, because of the sequencing, C1 does not get fully charged up in order to support a high side turn on.  If the power is cycled off then back on again, C1 is then charged up enough to turn on Q1 when the EN signal goes high.

    Does this make sense/is this a possibility?  Do you have any suggestion on what would be the best way to test this theory?

    Regards,

    Jeff

  • Hi Jeff,

    Closing this thread to respond over message.

    Thanks,

    Walter

  • Confirmed: because of the power up sequencing of the ENBL, VIN, VLO, and PWM IN, Q2 is not performing an initial turn-on to charge up C1.  Then, when the ENBL signal goes high, there is no voltage on C1 to drive the high-side FET.

    Thank you, Walter, for helping sort this out.