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TPS3850: Latching WDO with open drain buffer

Part Number: TPS3850
Other Parts Discussed in Thread: SN74LVC1G07, TLV7041

Tool/software:

Hi team,

My customer tried to implement WDO latch referring below thread.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1298948/tps3850-q1-latching-wdo-watchdog-output 

However, when he placed SN74LVC1G07DKCR(open drain buffer) between WDO and CRST, WDO  latch didn't work. Meanwhile, when they added 2pcs of N-ch FET on output to emulate external open drain buffer, WDO latch worked as expected.

Do you have any idea why adding only open drain buffer doesn't work?

Of course, he confirmed SN74LVC1G07DKCR with standalone operation works fine.

He used 1.8V for power supply of the buffer and TPS3850.

Best regards,

Shota Mago

  • Hi Shota,

    Can you verify if the output of the SN74LVC1G07 is able to pull CRST all the way to 0V? For this application, the latch is implemented by preventing the internal capacitor from charging. Also, what is the pull-up resistor value for the WDO?

    Jesse 

  • Hi Jesse,

    Maybe I found cause of this issue. Leakage current of the logic buffer is much larger than CRST pin charge current of TPS3850. This prevents correct operation.

    I ran some simulation using PSPICE for TI. When open drain comparator(TLV7041) which has low output leakage current, WDO latch worked as expected.

    TPS3850_WDO_Latch_Sim.pdf

    Best regards,

    Shota Mago

  • Hi Jesse,

    I have update for this inquiry. In addition to low leakage comparator/buffer, a capacitor is needed on CRST pin for latching WDO operation since NC and pull-up to VDD of CRST pin seem don't activate CRST charge current as these mode use factory programmed reset delay.

    The customer confirmed latching WDO works as expected when a capacitor on CRST pin and TLV7041 are used.

    Best regards,

    Shota Mago