Tool/software:
Dear Sirs and Madams,
We use the TPS51200 as a power supply for DDR.
In designs that comply with the restriction "keep total capacitance on REFOUT pin below 0.47 μF" in the datasheet, cases have been confirmed in which overshoots exceeding the DDR3/4 specifications occur.
This issue has been reported in many E2E design support articles:
There are several other similar reports as well.
All of the responses from TI engineers, including the one above, suggest using a capacitance much larger than 0.47μF (100μF in some cases) to suppress overshoot, which contradicts the description in the datasheet.
Regarding this matter, I would appreciate it if you could tell me the following points:
1. Could you please tell us the background and advantages of adding "keep total capacitance on REFOUT pin below 0.47 μF" to the datasheet?
Why was the above sentence added to the data sheet in 2016?
2. A design using a large-capacity (e.g. 100μF) capacitor, as recommended by a TI engineer in E2E, does not meet the datasheet specifications, but is this an official solution?
3. In a design that complies with the capacitor capacity of 0.47uF specified in the data sheet and has only a DDR load (overshoot can be suppressed by adding a resistive load, but wasteful power consumption occurs), overshoot at the REFOUT output is almost inevitable, as in the case of E2E.
Regarding this point, if TI has any opinions or materials regarding the impact on DDR (e.g., the impact is not a problem), could you please provide it to us?
Regards,
Masashi