I am using CSD16323Q3 having ultra low Qg in POL, it shows higher efficiency due to fast gate drive than other competitors.
However it shows high FET spike so it needs FET snubber, it shows high output voltage noise so it needs more filter capacitances.
Currently the PWB trace of between input line GND and source pin of bottom FET can not be shorten due to small PWB size and fixed pin out location.
I tried a slow FET having Qg=27nC, it shows less spike at most area but less efficiency as expected.
So is there any idea to get benifies of both high efficiency and less noise? Thanks.