We are having problems with cascading TLC5941's. We have 16 cascaded, but partway down the line they start getting incorrect data. This appears to be due to skewing of the clock pulse (which is just bussed to every part as shown in the data sheet). It doesn't take much distortion of the clock before the chip clocks in the previous data bit state rather than the one which has just shifted out. It looks like you really need to buffer the clock for each 1 or 2 devices but I can't see any reference to this anywhere. Is there a recommendation for clock distribution on these devices The clock is about 1MHz but it makes no difference what the speed is, it is down to how fast the clock edge rises.