I was looking at the EVM design and noticed that on the output grounds and both voltage outputs there is a split in the copper pour going to the headers (J4-J7). I haven't seen that done before and wondered why the board was designed like this.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I was looking at the EVM design and noticed that on the output grounds and both voltage outputs there is a split in the copper pour going to the headers (J4-J7). I haven't seen that done before and wondered why the board was designed like this.
The "point of regulation" is the possitive side of the output capacitors for each channel. The traces to the output headers are split to facilitate efficiency measurments. One side is inteded to carry the load currents, while the other is a remote sense so that a meeter can be connected directly to the point of load ithout the IR losses of the load.
Thanks John. That's interesting. I've looked at a lot of your eval boards and either I've missed it in the past or this design differs from others.
It varies a lot by product line. I tend not to do that in my EVMs as usually the point of load is very close to the board edge anyway. I do have some that use it though. I think you will find it more often in TPS6xxxx devices.