BQ24610 strange operation

After looking at your schematic, you are not using ACDRV.  ACDRV and BATDRV are out of phase and keep the battery and input from shoring together.  I wonder if you have a timing issue between the on/off of the ACFETs and BATFETs.

I see you put in N-CH FETs for the input and it has its own control.

Maybe you could use ACDRV to enable U1.

You could use a N-CH FET, gate connected to ACDRV, Drain connected to U1-8 and Source to ground.

Would need waveforms of the of the switching circuits to see what is going on.

Dear Charles,

thanks for your help!

I will try to add the NFET and update.

which waveforms are interesting for you?

how do you explain the behavior now? what would not work properly in your opinion?

since, everything seems to function properly (or is it?)...

regards,

Dear Charles,

I'm sensing that the inductor is getting really hot, when I'm withdrawing current to Load from the battery.

it is hotter that the transistor next to it, so I'm guessing he is the source of heat.

is this a side effect of the BATFET not being managed by the IC?

could it be that the current has a loop going into the IC through the inductor as well?

regards,

Since your configuration is different than the typical application I am not sure of the issues.

My main concern is that you have both the BAT FET and ACFETs on at the same time creating high current flow.

The other issue is if the input voltage goes way and the IC does not detect a sleep condition, it will keep the battery FET off and now the load is supplied by the battery going through the top FET's body diode via the inductor.

Would think that the top FET would get hot also.

It would be helpful to have a couple of current probes and measure where the current is going.

Also look at the gate drives of the ACFET and BATFET to see when these FETS are on.

I believe your best bet is to use the ACDRV and BATDRV to drive on/off the FETs to keep these waveforms "out of phase", to avoid shorting and oscillation issues.

Dear Charles,

I made the test with the N-FET.

it has stopped those oscillations I was talking about, but also current flow.
here is a table that describes the status:

when I place a load on the system, it discharges from the battery only, 13.17V or 12.56V.

I assume it is running through the diode of the BATFET because of the ~.5V voltage drop.
what is strange is why the ACFET pin turns on? this means I can never get a DC input...

any idea? do you see any misbehavior?

many thanks!

I am going to need some waveforms as requested earlier to see the gate drives, Vin_switched, Vsys, Vbat and current probes showing where the current is going to give more advice.

Dear Charles,

at this point, no current is flowing in the circuit anywhere...

and the waveform I made as you request shows exactly a ramp like the table on the last reply.

I have a thought I'd like to share:
when looking in the SCH of the EVM, I can see that the intended FET on the input are PFET.
when an input is felt on ACN, ACFET and VCC both are ~9V, allowing the PFET's Vgs to be 0V thus open.
in my SCH, I have the LTC4365 with NFETs. and I added an NFET to invert ACDRV, so 9V will give me no input.
so:

1. by this logic, I should connect ACDRV straight to pin 8 of the LTC4365 to have input, right?
   since '1' logic to this pin opens the flow.
2. what should I do with VCC connection? I cannot have it stable 9V on the source of my input NFET.
   can I connect it straight on DCin? I will loose reverse polarity protection won't I?

thanks for you thoughts and help

Dear Charles,

just to emphasize a point...
we are using BQ24610 in 2 big project that are waiting for production,

it is very important that I can use the LTC4365 with them since I need to control specific UV, OV events without adding another set of FETs (datasheet attached). 
I connected the ACDRV directly to !SHDN pin of LTC4365, and disconnected VCC from the sources of the input FETs (disconnected R21).
I get oscillations on the FETs since the GATE holds 9V and the source holds ~11V (I guess it is the battery after Q2, Q4, Q5 schlocky diodes), which is not high enough than Vgs=2.5V.

1. not sure if I did the right thing with VCC.
2. maybe I can have a voltage divider (or 5V Zener) on the input FETs gate to have a stronger ON mode.

please tell me about any test experiment that you think can help determine the problem.

many thanks,

My guess is that it is the LTC4365.

I think you have it configured correctly, as far as the gate drive, but there is a 800us delay after enabling the part...see shutdown section of LTC part.

I would also set the UV limit much lower until you get it working.

Probably need to keep the LTC4356 enabled all the time and clamp the AC FET gates to the source when you want them off by using the ACDRV as a trigger.

Dear Charles,

thanks a lot for your patience, I feel that we are close for solution.

I attached a revised SCH, please offer your opinion.

what still worries me is the oscillation that occurs.
it will happen every time VCC will be high as well as LTC4365 gate, I will get an oscillation.

1. what are the voltage level VCC can be? from what I've seen, it is:
   no DC input: same as ACDRV ~9V or ~0.4V
   DC input: same as DC input (in order to check OV and other events).

if this is right, then the 800uSec delay causes the oscillation, and I can be sure it won't return.
is it?

thanks again!

Dear Charles,

please discard the last schematics, obviously a mistake to use Pfet, I attached a new schematics with a Nfet.
I also added a Zener Diode in order to fix a lower voltage on the input transistors gate.
this stopped the oscillations, but did not make the system function.

here are the results:

you can see that anyway the VCC and ACDRV pin are the same.
so, how does the PFETs of the original AN even closes?
what is the normal operation of VCC,ACDRV,BATDRV when DCin off and on?

on DCin off mode, the battery fet closes for some reason. but I can still see the battery voltage through the schottky diode on the output? why is that? any idea? the FET is supposed to be wide open when there is no input.

thanks a lot!

thanks,

Dear Charles,

I wonder if the fact that in N-FETs the schottky diodes are facing the opposite way causes all the problems.
they allow the voltage from the battery to reach the VCC and wake up the chip, which causes all the problems.

should a healthy schotky diode over the right N-FET maybe solve all issues?

The source should connect to each other so that you need only one gate drive.

I see two issues, (1) the N-ch Q6 can't be driven on with ACDRV (P-CH drive); (2) why is U1 pin 5 not above the VCC source voltage.  It has to be higher than the Vcc to turn on the N-CH FETS.

Use attached drive for N-CH FETs.

Dear Charles,

thank you very much,

where should the VCC line be in your suggested schematics? on the common source of the FETs?

Yes, this is the reference point for driving the P-CH FETs gate drive.

Thanks for your feedback